公开(公告)号：US20190066815A1

公开(公告)日：2019-02-28

申请号：US15879455

申请日：2018-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Hsu Chiu ,  Shih-Feng Huang ,  Yi-Sin Wang ,  Arjit Ashok

IPC: G11C29/14 ,  G11C29/00 ,  G11C29/02 ,  G11C29/38 ,  G11C29/50 ,  G01R31/26 ,  G01R31/27

Abstract: The disclosure is related a method for testing and measuring the performances of electrical components on a semiconductor IC device through a test apparatus (also referred to as a testline) disposed in a scribe line between the semiconductor IC devices on a wafer. The test apparatus may include a built-in self-test (BIST) circuit and a duplication of the electrical components subjected to the performance measurement. Minimum and maximum testing voltages are provided to the test apparatus, where the range of voltage between the minimum and maximum testing voltages are divided into a plurality of testing operational voltages which are applied to the test apparatus. For each testing operational voltages, a memory array operation test is performed, where at least one of the testing operational voltages resulting in a performance failure is identified as the minimal operating voltage of the memory array.

公开(公告)号：US10319456B2

公开(公告)日：2019-06-11

申请号：US15879455

申请日：2018-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Hsu Chiu ,  Shih-Feng Huang ,  Yi-Sin Wang ,  Arjit Ashok

IPC: G11C7/00 ,  G11C29/00 ,  G11C29/14 ,  G11C29/02 ,  G01R31/27 ,  G11C29/50 ,  G01R31/26 ,  G11C29/38

Abstract: The disclosure is related a method for testing and measuring the performances of electrical components on a semiconductor IC device through a test apparatus (also referred to as a testline) disposed in a scribe line between the semiconductor IC devices on a wafer. The test apparatus may include a built-in self-test (BIST) circuit and a duplication of the electrical components subjected to the performance measurement. Minimum and maximum testing voltages are provided to the test apparatus, where the range of voltage between the minimum and maximum testing voltages are divided into a plurality of testing operational voltages which are applied to the test apparatus. For each testing operational voltages, a memory array operation test is performed, where at least one of the testing operational voltages resulting in a performance failure is identified as the minimal operating voltage of the memory array.