公开(公告)号：US20170110420A1

公开(公告)日：2017-04-20

申请号：US15051197

申请日：2016-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yu Cheng ,  Chih-Ping Chao ,  Kuan-Chi Tsai ,  Shih-Shiung Chen ,  Wei-Kung Tsai

IPC: H01L23/66 ,  H01L29/10 ,  H01L23/48 ,  H01L23/31 ,  H01L27/12 ,  H01L21/683 ,  H01L23/00 ,  H01L21/28 ,  H01L21/84 ,  H01L21/762 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/66 ,  H01L21/28008 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5225 ,  H01L23/528 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L27/1211 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1266 ,  H01L29/1079 ,  H01L2221/68368 ,  H01L2224/05025

Abstract: Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.

公开(公告)号：US20170062452A1

公开(公告)日：2017-03-02

申请号：US14840155

申请日：2015-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yong-En Syu ,  Kuan-Chi Tsai ,  Kuo-Yu Cheng ,  Keng-Yu Chen ,  Shih-Shiung Chen ,  Shao-Yu Chen ,  Wei-Kung Tsai ,  Yu-Lung Yeh

IPC: H01L27/115 ,  H01L29/06 ,  H01L29/423 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11573 ,  H01L21/84 ,  H01L27/11575 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: The present disclosure relates to a semiconductor substrate including, a first silicon layer comprising an upper surface with protrusions extending vertically with respect to the upper surface. An isolation layer is arranged over the upper surface meeting the first silicon layer at an interface, and a second silicon layer is arranged over the isolation layer. A method of manufacturing the semiconductor substrate is also provided.

Abstract translation: 本公开涉及一种半导体衬底，其包括第一硅层，第一硅层包括具有相对于上表面垂直延伸的突起的上表面。 隔离层设置在界面上与第一硅层相遇的上表面上，并且第二硅层布置在隔离层之上。 还提供了制造半导体衬底的方法。

公开(公告)号：US20200058608A1

公开(公告)日：2020-02-20

申请号：US16662391

申请日：2019-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yu Cheng ,  Chih-Ping Chao ,  Kuan-Chi Tsai ,  Shih-Shiung Chen ,  Wei-Kung Tsai

IPC: H01L23/66 ,  H01L27/12 ,  H01L23/528 ,  H01L23/48 ,  H01L21/84 ,  H01L21/768 ,  H01L21/683 ,  H01L23/522

Abstract: Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.

公开(公告)号：US09799557B2

公开(公告)日：2017-10-24

申请号：US14161208

申请日：2014-01-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yu Cheng ,  Wei-Kung Tsai ,  Kuan-Chi Tsai

IPC: H01L21/768 ,  H01L27/02 ,  H01L29/06 ,  H01L23/58 ,  H01L21/311 ,  H01L21/84 ,  H01L21/74

CPC classification number: H01L21/76877 ,  H01L21/31144 ,  H01L21/743 ,  H01L21/76816 ,  H01L21/84 ,  H01L23/585 ,  H01L27/0248 ,  H01L29/0607 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: In accordance with some embodiments, a semiconductor device is provided. The semiconductor device structure includes a substrate, and the substrate has a device region and an edge region. The semiconductor device structure also includes a silicon layer formed on the substrate and a transistor formed on the silicon layer. The transistor is formed at the device region of the substrate. The semiconductor device structure further includes a metal ring formed in the silicon layer. The metal ring is formed at the edge region of the substrate, and the transistor is surrounded by the metal ring.

公开(公告)号：US09711521B2

公开(公告)日：2017-07-18

申请号：US14840155

申请日：2015-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yong-En Syu ,  Kuan-Chi Tsai ,  Kuo-Yu Cheng ,  Keng-Yu Chen ,  Shih-Shiung Chen ,  Shao-Yu Chen ,  Wei-Kung Tsai ,  Yu-Lung Yeh

IPC: H01L29/06 ,  H01L27/11573 ,  H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L27/11575

CPC classification number: H01L27/11573 ,  H01L21/84 ,  H01L27/11575 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: The present disclosure relates to a semiconductor substrate including, a first silicon layer comprising an upper surface with protrusions extending vertically with respect to the upper surface. An isolation layer is arranged over the upper surface meeting the first silicon layer at an interface, and a second silicon layer is arranged over the isolation layer. A method of manufacturing the semiconductor substrate is also provided.

公开(公告)号：US11121098B2

公开(公告)日：2021-09-14

申请号：US15696532

申请日：2017-09-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yu Cheng ,  Chih-Ping Chao ,  Kuan-Chi Tsai ,  Shih-Shiung Chen ,  Wei-Kung Tsai

IPC: H01L23/66 ,  H01L23/522 ,  H01L21/768 ,  H01L27/12 ,  H01L21/683 ,  H01L21/84 ,  H01L23/48 ,  H01L23/528 ,  H01L23/552

Abstract: Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.

公开(公告)号：US09048287B1

公开(公告)日：2015-06-02

申请号：US14081624

申请日：2013-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yu Cheng ,  Wei-Kung Tsai ,  Kuan-Chi Tsai

IPC: H01L27/12 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/7624 ,  H01L21/76829 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/78654

Abstract: Embodiments of mechanisms for forming a semiconductor device structure with floating spacers are provided. The semiconductor device structure includes a silicon-on-insulator (SOI) substrate and a gate stack formed on the SOI substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stack. The gate spacers include a floating spacer. The semiconductor device structure further includes a contact etch stop layer formed on the gate stack and the gate spacers. The contact etch stop layer is formed between the floating spacer and the SOI substrate.

Abstract translation: 提供了用于形成具有浮动间隔件的半导体器件结构的机构的实施例。 半导体器件结构包括在SOI衬底上形成的绝缘体上硅（SOI）衬底和栅叠层。 半导体器件结构还包括形成在栅极堆叠的侧壁上的栅极间隔物。 栅极间隔物包括浮动间隔物。 半导体器件结构还包括形成在栅极堆叠和栅极间隔物上的接触蚀刻停止层。 接触蚀刻停止层形成在浮动间隔物和SOI衬底之间。

公开(公告)号：US11121100B2

公开(公告)日：2021-09-14

申请号：US16662391

申请日：2019-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yu Cheng ,  Chih-Ping Chao ,  Kuan-Chi Tsai ,  Shih-Shiung Chen ,  Wei-Kung Tsai

IPC: H01L23/66 ,  H01L23/522 ,  H01L21/768 ,  H01L27/12 ,  H01L21/683 ,  H01L21/84 ,  H01L23/48 ,  H01L23/528 ,  H01L23/552

Abstract: Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.

公开(公告)号：US10090327B2

公开(公告)日：2018-10-02

申请号：US14158430

申请日：2014-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yu Cheng ,  Keng-Yu Chen ,  Wei-Kung Tsai ,  Kuan-Chi Tsai ,  Tsung-Yu Yang ,  Chung-Long Chang ,  Chun-Hung Chen ,  Chih-Ping Chao

IPC: H01L27/12 ,  H01L27/06 ,  H01L21/306 ,  H01L21/311 ,  H01L21/28 ,  H01L23/66 ,  H01L21/762 ,  H01L21/02 ,  H01L49/02 ,  H01L21/84 ,  H01L21/763 ,  H01L23/522

Abstract: Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a buried oxide layer formed over the substrate. An interface layer is formed between the substrate and the buried oxide layer. The semiconductor device structure also includes a silicon layer formed over the buried oxide layer; and a polysilicon layer formed over the substrate and in a deep trench. The polysilicon layer extends through the silicon layer, the buried oxide layer and the interface layer.

公开(公告)号：US20180012850A1

公开(公告)日：2018-01-11

申请号：US15696532

申请日：2017-09-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yu Cheng ,  Chih-Ping Chao ,  Kuan-Chi Tsai ,  Shih-Shiung Chen ,  Wei-Kung Tsai

IPC: H01L23/66 ,  H01L21/683 ,  H01L21/762 ,  H01L21/768 ,  H01L29/10 ,  H01L23/00 ,  H01L23/528 ,  H01L21/28 ,  H01L23/48 ,  H01L23/31 ,  H01L21/84 ,  H01L23/522 ,  H01L27/12 ,  H01L23/552

CPC classification number: H01L23/66 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5225 ,  H01L23/528 ,  H01L23/552 ,  H01L27/1211 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2224/05025

Abstract: Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.