知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.017 seconds)

    HANDLE WAFER FOR HIGH RESISTIVITY TRAP-RICH SOI
    1.
    发明申请
    HANDLE WAFER FOR HIGH RESISTIVITY TRAP-RICH SOI 有权
    用于高电阻TRAP-RICH SOI的手柄波形

    公开(公告)号：US20150270143A1

    公开(公告)日：2015-09-24

    申请号：US14222785

    申请日：2014-03-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Alex Kalnitsky ,  Chung-Long Chang ,  Yung-Chih Tsai ,  Tsung-Yu Yang ,  Keng-Yu Chen ,  Yong-En Syu

    IPC: H01L21/322 ,  H01L29/34 ,  H01L27/12

    CPC classification number: H01L21/3226 ,  H01L21/26506 ,  H01L21/304 ,  H01L21/3046 ,  H01L21/32105 ,  H01L21/7624 ,  H01L27/1203 ,  H01L29/34

    Abstract: The present disclosure relates to a silicon-on-insulator (SOI) substrate having a trap-rich layer, with crystal defects, which is disposed within a handle wafer, and an associated method of formation. In some embodiments, the SOI substrate has a handle wafer. A trap-rich layer, having a plurality of crystal defects that act to trap carriers, is disposed within the handle wafer at a position abutting a top surface of the handle wafer. An insulating layer is disposed onto the handle wafer. The insulating layer has a first side abutting the top surface of the handle wafer and an opposing second side abutting a thin layer of active silicon. By forming the trap-rich layer within the handle wafer, fabrication costs associated with depositing a trap-rich material (e.g., polysilicon) onto a handle wafer are reduced and thermal instability issues are prevented.

    Abstract translation: 本公开内容涉及具有富集陷阱层的绝缘体上硅（SOI）衬底，其具有设置在处理晶片内的晶体缺陷以及相关联的形成方法。 在一些实施例中，SOI衬底具有处理晶片。 在与处理晶片的顶表面相邻的位置处，在处理晶片内设置具有多个用于捕获载流子的晶体缺陷的富含阱的层。 绝缘层设置在手柄晶片上。 绝缘层具有邻接手柄晶片的顶表面的第一侧和与活性硅薄层邻接的相对的第二侧。 通过在处理晶片内形成富含阱的层，减少了将富含陷阱的材料（例如多晶硅）沉积到处理晶片上的制造成本，并防止了热不稳定性问题。

    SOI SUBSTRATE
    3.
    发明申请
    SOI SUBSTRATE 审中-公开

    公开(公告)号：US20190259655A1

    公开(公告)日：2019-08-22

    申请号：US16405165

    申请日：2019-05-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Ming-Che Yang ,  Wei-Kung Tsai ,  Yong-En Syu ,  Yeur-Luen Tu ,  Chris Chen

    IPC: H01L21/762 ,  H01L29/06 ,  H01L29/16

    Abstract: The present disclosure, in some embodiments, relates to a silicon on insulator (SOI) substrate. The SOI substrate includes a dielectric layer disposed over a first substrate. The dielectric layer has an outside edge aligned with an outside edge of the first substrate. An active layer covers a first annular portion of an upper surface of the dielectric layer. The upper surface of the dielectric layer has a second annular portion that surrounds the first annular portion and extends to the outside edge of the dielectric layer. The second annular portion is uncovered by the active layer.

    PROCESS TO FORM SOI SUBSTRATE
    5.
    发明申请
    PROCESS TO FORM SOI SUBSTRATE 审中-公开

    公开(公告)号：US20190157138A1

    公开(公告)日：2019-05-23

    申请号：US15904915

    申请日：2018-02-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Ming-Che Yang ,  Wei-Kung Tsai ,  Yong-En Syu ,  Yeur-Luen Tu ,  Chris Chen

    IPC: H01L21/762 ,  H01L29/06 ,  H01L29/16

    Abstract: The present disclosure, in some embodiments, relates to a method of forming an SOI substrate. The method may be performed by epitaxially forming a silicon-germanium (SiGe) layer over a sacrificial substrate and epitaxially forming a first active layer on the SiGe layer. The first active layer has a composition different than the SiGe layer. The sacrificial substrate and is flipped and the first active layer is bonded to an upper surface of a dielectric layer formed over a first substrate. The sacrificial substrate and the SiGe layer are removed and the first active layer is etched to define outermost sidewalls and to expose an outside edge of an upper surface of the dielectric layer. A contiguous active layer is formed by epitaxially forming a second active layer on the first active layer. The first active layer and the second active layer have a substantially same composition.

    Handle wafer for high resistivity trap-rich SOI
    7.
    发明授权
    Handle wafer for high resistivity trap-rich SOI 有权
    处理高电阻阱富集SOI的晶圆

    公开(公告)号：US09269591B2

    公开(公告)日：2016-02-23

    申请号：US14222785

    申请日：2014-03-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Alex Kalnitsky ,  Chung-Long Chang ,  Yung-Chih Tsai ,  Tsung-Yu Yang ,  Keng-Yu Chen ,  Yong-En Syu

    IPC: H01L21/322 ,  H01L27/12 ,  H01L29/34

    CPC classification number: H01L21/3226 ,  H01L21/26506 ,  H01L21/304 ,  H01L21/3046 ,  H01L21/32105 ,  H01L21/7624 ,  H01L27/1203 ,  H01L29/34

    Abstract: The present disclosure relates to a silicon-on-insulator (SOI) substrate having a trap-rich layer, with crystal defects, which is disposed within a handle wafer, and an associated method of formation. In some embodiments, the SOI substrate has a handle wafer. A trap-rich layer, having a plurality of crystal defects that act to trap carriers, is disposed within the handle wafer at a position abutting a top surface of the handle wafer. An insulating layer is disposed onto the handle wafer. The insulating layer has a first side abutting the top surface of the handle wafer and an opposing second side abutting a thin layer of active silicon. By forming the trap-rich layer within the handle wafer, fabrication costs associated with depositing a trap-rich material (e.g., polysilicon) onto a handle wafer are reduced and thermal instability issues are prevented.

    Abstract translation: 本公开内容涉及具有富集陷阱层的绝缘体上硅（SOI）衬底，其具有设置在处理晶片内的晶体缺陷以及相关联的形成方法。 在一些实施例中，SOI衬底具有处理晶片。 在与处理晶片的顶表面相邻的位置处，在处理晶片内设置具有多个用于捕获载流子的晶体缺陷的富含阱的层。 绝缘层设置在手柄晶片上。 绝缘层具有邻接手柄晶片的顶表面的第一侧和与活性硅薄层邻接的相对的第二侧。 通过在处理晶片内形成富含阱的层，减少了将富含陷阱的材料（例如多晶硅）沉积到处理晶片上的制造成本，并防止了热不稳定性问题。

    Process to form SOI substrate
    9.
    发明授权
    Process to form SOI substrate 有权

    公开(公告)号：US10304723B1

    公开(公告)日：2019-05-28

    申请号：US15904915

    申请日：2018-02-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Ming-Che Yang ,  Wei-Kung Tsai ,  Yong-En Syu ,  Yeur-Luen Tu ,  Chris Chen

    IPC: H01L21/762 ,  H01L29/06 ,  H01L29/16 ,  H01L27/12 ,  H01L21/84

    Abstract: The present disclosure, in some embodiments, relates to a method of forming an SOI substrate. The method may be performed by epitaxially forming a silicon-germanium (SiGe) layer over a sacrificial substrate and epitaxially forming a first active layer on the SiGe layer. The first active layer has a composition different than the SiGe layer. The sacrificial substrate and is flipped and the first active layer is bonded to an upper surface of a dielectric layer formed over a first substrate. The sacrificial substrate and the SiGe layer are removed and the first active layer is etched to define outermost sidewalls and to expose an outside edge of an upper surface of the dielectric layer. A contiguous active layer is formed by epitaxially forming a second active layer on the first active layer. The first active layer and the second active layer have a substantially same composition.

Patent Agency Ranking