Method for forming image sensor device

    公开(公告)号:US10734427B2

    公开(公告)日:2020-08-04

    申请号:US16277375

    申请日:2019-02-15

    Abstract: A method for forming an image sensor device is provided. The method includes providing a semiconductor substrate including a front surface, a back surface opposite to the front surface, at least one light-sensing region close to the front surface, and a first trench surrounding the light-sensing region. The method includes forming an insulating layer over the back surface and in the first trench. A void is formed in the insulating layer in the first trench, and the void is closed. The method includes removing the insulating layer over the void to open up the void. The opened void forms a second trench partially in the first trench. The method includes filling a reflective structure in the second trench. The reflective structure has a light reflectivity ranging from about 70% to about 100%.

    CMOS image sensor with dual damascene grid design having absorption enhancement structure

    公开(公告)号:US10153319B2

    公开(公告)日:2018-12-11

    申请号:US15960780

    申请日:2018-04-24

    Abstract: The present disclosure, in some embodiments, relates to a method of forming an image sensor integrated chip. The method may be performed by forming an image sensing element within a substrate, and forming an absorption enhancement structure over a back-side of the substrate. The absorption enhancement structure is selectively etched to concurrently define a plurality of grid structure openings and a ground structure opening within the absorption enhancement structure. A grid structure is formed within the plurality of grid structure openings and a ground structure is formed within the ground structure opening. The grid structure extends from over the absorption enhancement structure to a location within the absorption enhancement structure.

    QE approach by double-side, multi absorption structure

    公开(公告)号:US10553733B2

    公开(公告)日:2020-02-04

    申请号:US15716714

    申请日:2017-09-27

    Abstract: The present disclosure relates to an integrated chip that has a light sensing element arranged within a substrate. An absorption enhancement structure is arranged along a back-side of the substrate, and an interconnect structure is arranged along a front-side of the substrate. A reflection structure includes a dielectric structure and a plurality of semiconductor pillars that matingly engage the dielectric structure. The dielectric structure and semiconductor pillars are arranged along the front-side of the substrate and are spaced between the light sensing element and the interconnect structure. The plurality of semiconductor pillars and the dielectric structure are collectively configured to reflect incident light that has passed through the absorption enhancement structure and through the light sensing element back towards the light sensing element before the incident light strikes the interconnect structure.

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