公开(公告)号：US09263437B2

公开(公告)日：2016-02-16

申请号：US14133037

申请日：2013-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh-Shuo Liang ,  Hsing-Chih Lin ,  Yu-Lung Yeh ,  Chih-Ho Tai ,  Ching-Hung Huang

IPC: H01L29/78 ,  H01L27/06 ,  H01L23/522 ,  H01L49/02 ,  H01L23/532

CPC classification number: H01L27/0688 ,  H01L23/5223 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of mechanisms for forming a metal-insulator-metal (MIM) capacitor structure are provided. The metal-insulator-metal capacitor structure includes a substrate. The MIM capacitor structure also includes a CBM layer formed on the substrate, and the CBM layer includes a bottom barrier layer, a main metal layer and a top barrier layer. The MIM capacitor structure further includes a first high-k dielectric layer formed on the CBM layer, an insulating layer formed on the first high-k dielectric layer and a second high-k dielectric layer formed on the insulating layer. The MIM capacitor structure also includes a CTM layer formed on the second high-k dielectric layer, and the CBM layer includes a bottom barrier layer, a main metal layer and a top barrier layer.

Abstract translation: 提供了用于形成金属 - 绝缘体 - 金属（MIM）电容器结构的机构的实施例。 金属 - 绝缘体 - 金属电容器结构包括基板。 MIM电容器结构还包括在衬底上形成的CBM层，并且CBM层包括底部阻挡层，主金属层和顶部阻挡层。 MIM电容器结构还包括形成在CBM层上的第一高k电介质层，形成在第一高k电介质层上的绝缘层和形成在绝缘层上的第二高k电介质层。 MIM电容器结构还包括形成在第二高k电介质层上的CTM层，并且CBM层包括底部阻挡层，主金属层和顶部阻挡层。

公开(公告)号：US20210273038A1

公开(公告)日：2021-09-02

申请号：US16807034

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Liang Chen ,  Yu-Lung Yeh ,  Chihchous Chuang ,  Yen-Hsiu Chen ,  Tsai-Ji Liou ,  Yung-Hsiang Chen ,  Ching-Hung Huang

IPC: H01L49/02 ,  H01L21/02 ,  H01J37/32 ,  C23C16/50 ,  C23C16/40

Abstract: A semiconductor processing system is provided to form a capacitor dielectric layer in a metal-insulator-metal capacitor. The semiconductor processing system includes a precursor tank configured to generate a precursor gas from a metal organic solid precursor, a processing chamber configured to perform a plasma enhanced chemical vapor deposition, and at least one buffer tank between the precursor tank and the processing chamber. The at least one buffer tank is coupled to the precursor tank via a first pipe and coupled to the processing chamber via a second pipe.

公开(公告)号：US11502160B2

公开(公告)日：2022-11-15

申请号：US16807034

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Liang Chen ,  Yu-Lung Yeh ,  Chihchous Chuang ,  Yen-Hsiu Chen ,  Tsai-Ji Liou ,  Yung-Hsiang Chen ,  Ching-Hung Huang

IPC: H01L21/02 ,  H01L49/02 ,  H01J37/32 ,  C23C16/50 ,  C23C16/40

Abstract: A semiconductor processing system is provided to form a capacitor dielectric layer in a metal-insulator-metal capacitor. The semiconductor processing system includes a precursor tank configured to generate a precursor gas from a metal organic solid precursor, a processing chamber configured to perform a plasma enhanced chemical vapor deposition, and at least one buffer tank between the precursor tank and the processing chamber. The at least one buffer tank is coupled to the precursor tank via a first pipe and coupled to the processing chamber via a second pipe.

公开(公告)号：US09543152B2

公开(公告)日：2017-01-10

申请号：US14322501

申请日：2014-07-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ching-Hung Huang ,  Bo-Chang Su ,  Chih-Ho Tai ,  Wen-Tsao Chen ,  Kuan-Chi Tsai

IPC: H01L49/02 ,  H01L21/263 ,  H01L21/311

CPC classification number: H01L21/263 ,  H01L21/02071 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32139 ,  H01L28/60

Abstract: The semiconductor device includes a substrate, a bottom electrode, a capacitor dielectric layer, a top electrode, an etching stop layer, a first anti-reflective coating layer and a capping layer. The bottom electrode is on the substrate. The capacitor dielectric layer is on the bottom electrode. The capacitor dielectric layer has a first region and a second region adjacent to the first region. The top electrode is on the first region of the capacitor dielectric layer. The etching stop layer is on the top electrode. The first anti-reflective coating layer is on the etching stop layer, in which the first anti-reflective coating layer, the etching stop layer and the top electrode together have a sidewall. The capping layer overlies the sidewall, the etching stop layer, the second region of the capacitor dielectric layer, in which the capping layer is formed from oxide or nitride.

Abstract translation: 半导体器件包括衬底，底部电极，电容器电介质层，顶部电极，蚀刻停止层，第一抗反射涂层和覆盖层。 底部电极位于基板上。 电容器介质层位于底部电极上。 电容器介电层具有与第一区相邻的第一区和第二区。 顶部电极位于电容器介电层的第一区域上。 蚀刻停止层位于顶部电极上。 第一抗反射涂层位于蚀刻停止层上，其中第一抗反射涂层，蚀刻停止层和顶电极一起具有侧壁。 覆盖层覆盖侧壁，蚀刻停止层，电容器介电层的第二区域，其中覆盖层由氧化物或氮化物形成。

公开(公告)号：US09502494B2

公开(公告)日：2016-11-22

申请号：US14338042

申请日：2014-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chieh-Shuo Liang ,  Chih-Ho Tai ,  Ching-Hung Huang ,  Ying-Tsang Ho ,  Po-Jung Chiang

IPC: H01L27/12 ,  H01L49/02

CPC classification number: H01L28/75

Abstract: A metal-insulator-metal (MIM) capacitor structure and method for forming MIM capacitor structure are provided. The MIM capacitor structure includes a substrate and a metal-insulator-metal (MIM) capacitor formed on the substrate. The MIM capacitor includes a capacitor top metal (CTM) layer, a capacitor bottom metal (CBM) layer and an insulator formed between the CTM layer and the CBM layer. The insulator includes an insulating layer and a first high-k dielectric layer, and the insulating layer includes a nitride layer and an oxide layer, and the nitride layer is formed between the first high-k dielectric layer and the oxide layer.

Abstract translation: 提供一种用于形成MIM电容器结构的金属 - 绝缘体 - 金属（MIM）电容器结构和方法。 MIM电容器结构包括在基板上形成的基板和金属 - 绝缘体 - 金属（MIM）电容器。 MIM电容器包括电容器顶部金属（CTM）层，电容器底部金属（CBM）层和形成在CTM层和CBM层之间的绝缘体。 绝缘体包括绝缘层和第一高k电介质层，绝缘层包括氮化物层和氧化物层，并且氮化物层形成在第一高k电介质层和氧化物层之间。