公开(公告)号：US20190157138A1

公开(公告)日：2019-05-23

申请号：US15904915

申请日：2018-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Ming-Che Yang ,  Wei-Kung Tsai ,  Yong-En Syu ,  Yeur-Luen Tu ,  Chris Chen

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/16

Abstract: The present disclosure, in some embodiments, relates to a method of forming an SOI substrate. The method may be performed by epitaxially forming a silicon-germanium (SiGe) layer over a sacrificial substrate and epitaxially forming a first active layer on the SiGe layer. The first active layer has a composition different than the SiGe layer. The sacrificial substrate and is flipped and the first active layer is bonded to an upper surface of a dielectric layer formed over a first substrate. The sacrificial substrate and the SiGe layer are removed and the first active layer is etched to define outermost sidewalls and to expose an outside edge of an upper surface of the dielectric layer. A contiguous active layer is formed by epitaxially forming a second active layer on the first active layer. The first active layer and the second active layer have a substantially same composition.

公开(公告)号：US20140264559A1

公开(公告)日：2014-09-18

申请号：US13866102

申请日：2013-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Hong-Seng Shue ,  Kun-Ming Huang ,  Tzu-Cheng Chen ,  Ming-Che Yang ,  Po-Tao Chu

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7802 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/8238 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0634

Abstract: A method for forming a semiconductor device includes forming a hard mask layer over a substrate comprising a semiconductor material of a first conductivity type, and forming a plurality of trenches in the hard mask layer and extending into the substrate. Each trench has at least one side wall and a bottom wall. The method further includes forming at least one barrier insulator layer along the at least one side wall and over the bottom wall of each trench, removing the at least one barrier insulator layer over the bottom wall of each trench, and filling the plurality of trenches with a semiconductor material of a second conductivity type.

Abstract translation: 一种形成半导体器件的方法包括在包括第一导电类型的半导体材料的衬底上形成硬掩模层，并且在硬掩模层中形成并延伸到衬底中的多个沟槽。 每个沟槽具有至少一个侧壁和底壁。 该方法还包括沿着每个沟槽的至少一个侧壁和底壁上形成至少一个阻挡绝缘体层，在每个沟槽的底壁上去除至少一个阻挡绝缘体层，并且将多个沟槽填充到 第二导电类型的半导体材料。

公开(公告)号：US11063117B2

公开(公告)日：2021-07-13

申请号：US15492472

申请日：2017-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Yong-En Syu ,  Kuo-Hwa Tzeng ,  Ke-Dian Wu ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Ming-Che Yang ,  Wei-Kung Tsai

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66 ,  H01L29/15

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a supporting substrate. The semiconductor device structure also includes a first carrier-trapping layer covering the supporting substrate. The first carrier-trapping layer is doped with a group-IV dopant. The semiconductor device structure further includes an insulating layer covering the first carrier-trapping layer. In addition, the semiconductor device structure includes a semiconductor substrate over the insulating layer. The semiconductor device structure also includes a transistor. The transistor includes a gate stack over the semiconductor substrate and source and drain structures in the semiconductor substrate.

公开(公告)号：US20190259655A1

公开(公告)日：2019-08-22

申请号：US16405165

申请日：2019-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Ming-Che Yang ,  Wei-Kung Tsai ,  Yong-En Syu ,  Yeur-Luen Tu ,  Chris Chen

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/16

Abstract: The present disclosure, in some embodiments, relates to a silicon on insulator (SOI) substrate. The SOI substrate includes a dielectric layer disposed over a first substrate. The dielectric layer has an outside edge aligned with an outside edge of the first substrate. An active layer covers a first annular portion of an upper surface of the dielectric layer. The upper surface of the dielectric layer has a second annular portion that surrounds the first annular portion and extends to the outside edge of the dielectric layer. The second annular portion is uncovered by the active layer.

公开(公告)号：US08975153B2

公开(公告)日：2015-03-10

申请号：US13866102

申请日：2013-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Hong-Seng Shue ,  Kun-Ming Huang ,  Tzu-Cheng Chen ,  Ming-Che Yang ,  Po-Tao Chu

IPC: H01L21/02 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L29/7802 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/8238 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0634

Abstract: A method for forming a semiconductor device includes forming a hard mask layer over a substrate comprising a semiconductor material of a first conductivity type, and forming a plurality of trenches in the hard mask layer and extending into the substrate. Each trench has at least one side wall and a bottom wall. The method further includes forming at least one barrier insulator layer along the at least one side wall and over the bottom wall of each trench, removing the at least one barrier insulator layer over the bottom wall of each trench, and filling the plurality of trenches with a semiconductor material of a second conductivity type.

Abstract translation: 一种形成半导体器件的方法包括在包括第一导电类型的半导体材料的衬底上形成硬掩模层，并且在硬掩模层中形成并延伸到衬底中的多个沟槽。 每个沟槽具有至少一个侧壁和底壁。 该方法还包括沿着每个沟槽的至少一个侧壁和底壁上形成至少一个阻挡绝缘体层，在每个沟槽的底壁上去除至少一个阻挡绝缘体层，并且将多个沟槽填充到 第二导电类型的半导体材料。

公开(公告)号：US11158534B2

公开(公告)日：2021-10-26

申请号：US16405165

申请日：2019-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Ming-Che Yang ,  Wei-Kung Tsai ,  Yong-En Syu ,  Yeur-Luen Tu ,  Chris Chen

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/16 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02 ,  H01L21/311

Abstract: The present disclosure, in some embodiments, relates to a silicon on insulator (SOI) substrate. The SOI substrate includes a dielectric layer disposed over a first substrate. The dielectric layer has an outside edge aligned with an outside edge of the first substrate. An active layer covers a first annular portion of an upper surface of the dielectric layer. The upper surface of the dielectric layer has a second annular portion that surrounds the first annular portion and extends to the outside edge of the dielectric layer. The second annular portion is uncovered by the active layer.

公开(公告)号：US10304723B1

公开(公告)日：2019-05-28

申请号：US15904915

申请日：2018-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Ming-Che Yang ,  Wei-Kung Tsai ,  Yong-En Syu ,  Yeur-Luen Tu ,  Chris Chen

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/16 ,  H01L27/12 ,  H01L21/84

Abstract: The present disclosure, in some embodiments, relates to a method of forming an SOI substrate. The method may be performed by epitaxially forming a silicon-germanium (SiGe) layer over a sacrificial substrate and epitaxially forming a first active layer on the SiGe layer. The first active layer has a composition different than the SiGe layer. The sacrificial substrate and is flipped and the first active layer is bonded to an upper surface of a dielectric layer formed over a first substrate. The sacrificial substrate and the SiGe layer are removed and the first active layer is etched to define outermost sidewalls and to expose an outside edge of an upper surface of the dielectric layer. A contiguous active layer is formed by epitaxially forming a second active layer on the first active layer. The first active layer and the second active layer have a substantially same composition.