公开(公告)号：US10312207B2

公开(公告)日：2019-06-04

申请号：US15883797

申请日：2018-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hong Chang ,  Chun-Yi Yang ,  Kun-Ming Huang ,  Po-Tao Chu ,  Shen-Ping Wang ,  Chien-Li Kuo

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L23/31 ,  H01L23/29

Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

公开(公告)号：US09941384B2

公开(公告)日：2018-04-10

申请号：US14839931

申请日：2015-08-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jheng-Sheng You ,  Hsin-Chih Lin ,  Kun-Ming Huang ,  Lieh-Chuan Chen ,  Po-Tao Chu ,  Shen-Ping Wang ,  Chien-Li Kuo

IPC: H01L21/50 ,  H01L29/66 ,  H01L29/778 ,  H01L29/40 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/66462 ,  H01L29/1066 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/452 ,  H01L29/7786

Abstract: A semiconductor device includes a first III-V compound layer on a substrate, a second III-V compound layer on the first III-V compound layer, in which a material of the first III-V compound layer is different from that of the second III-V compound layer, a gate metal stack disposed on the second III-V compound layer, a source contact and a drain contact disposed at opposite sides of the gate metal stack, a gate field plate disposed between the gate metal stack and the drain contact, an anti-reflective coating (ARC) layer formed on the source contact and the drain contact, and an etch stop layer formed on the ARC layer.

公开(公告)号：US09698024B2

公开(公告)日：2017-07-04

申请号：US14330092

申请日：2014-07-14

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Long-Shih Lin ,  Fu-Hsiung Yang ,  Kun-Ming Huang ,  Ming-Yi Lin ,  Paul Chu

IPC: H01L21/308 ,  H01L29/66 ,  H01L29/78 ,  H01L29/739 ,  G01R31/12 ,  H01L29/08 ,  G01R31/26 ,  H01L21/762

CPC classification number: H01L21/308 ,  G01R31/129 ,  G01R31/2637 ,  H01L21/3083 ,  H01L21/76275 ,  H01L21/76283 ,  H01L29/086 ,  H01L29/66325 ,  H01L29/66689 ,  H01L29/7394 ,  H01L29/7824

Abstract: Some embodiments of the present disclosure relate to a method to increase breakdown voltage of a power device. A power device is formed on a silicon-on-insulator (SOI) wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer. A recess is formed in a lower surface of the handle wafer to define a recessed region of the handle wafer. The recessed region of the handle wafer has a first handle wafer thickness, which is greater than zero. An un-recessed region of the handle wafer has a second handle wafer thickness, which is greater than the first handle wafer thickness. The first handle wafer thickness of the recessed region provides a breakdown voltage improvement for the power device.

公开(公告)号：US09614031B2

公开(公告)日：2017-04-04

申请号：US14806854

申请日：2015-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Shou-Wei Lee ,  Shao-Chi Yu ,  Hong-Seng Shue ,  Kun-Ming Huang ,  Po-Tao Chu

IPC: H01L21/761 ,  H01L21/762 ,  H01L21/308 ,  H01L21/225 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/324 ,  H01L29/10

CPC classification number: H01L29/0634 ,  H01L21/2254 ,  H01L21/2257 ,  H01L21/308 ,  H01L21/324 ,  H01L21/761 ,  H01L21/76224 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811

Abstract: A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate.

公开(公告)号：US20140159103A1

公开(公告)日：2014-06-12

申请号：US13706975

申请日：2012-12-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD

Inventor： Long-Shih Lin ,  Fu-Hsiung Yang ,  Kun-Ming Huang ,  Ming-Yi Lin ,  Po-Tao Chu

IPC: H01L29/78 ,  H01L21/762

CPC classification number: H01L29/7824 ,  H01L21/6835 ,  H01L21/76202 ,  H01L21/76256 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/086 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66689 ,  H01L29/7394 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a method and apparatus to increase breakdown voltage of a semiconductor power device. A bonded wafer is formed by bonding a device wafer to a handle wafer with an intermediate oxide layer. The device wafer is thinned substantially from its original thickness. A power device is formed within the device wafer through a semiconductor fabrication process. The handle wafer is patterned to remove section of the handle wafer below the power device, resulting in a breakdown voltage improvement for the power device as well as a uniform electrostatic potential under reverse biasing conditions of the power device, wherein the breakdown voltage is determined. Other methods and structures are also disclosed.

Abstract translation: 本公开涉及一种增加半导体功率器件的击穿电压的方法和装置。 通过将器件晶片与具有中间氧化物层的手柄晶片结合来形成键合晶片。 器件晶片基本上从其原始厚度变薄。 通过半导体制造工艺在器件晶片内形成功率器件。 将处理晶片图案化以去除功率器件下方的处理晶片的部分，导致功率器件的击穿电压改善以及在功率器件的反向偏置条件下的均匀静电电势，其中确定击穿电压。 还公开了其它方法和结构。

公开(公告)号：US10804231B2

公开(公告)日：2020-10-13

申请号：US16419280

申请日：2019-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hong Chang ,  Chun-Yi Yang ,  Kun-Ming Huang ,  Po-Tao Chu ,  Shen-Ping Wang ,  Chien-Li Kuo

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L23/50 ,  H01L23/29

Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

公开(公告)号：US20190273059A1

公开(公告)日：2019-09-05

申请号：US16419280

申请日：2019-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hong Chang ,  Chun-Yi Yang ,  Kun-Ming Huang ,  Po-Tao Chu ,  Shen-Ping Wang ,  Chien-Li Kuo

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L23/522

Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

公开(公告)号：US20190019770A1

公开(公告)日：2019-01-17

申请号：US15883797

申请日：2018-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hong Chang ,  Chun-Yi Yang ,  Kun-Ming Huang ,  Po-Tao Chu ,  Shen-Ping Wang ,  Chien-Li Kuo

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L23/522

Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

公开(公告)号：US20140264559A1

公开(公告)日：2014-09-18

申请号：US13866102

申请日：2013-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Hong-Seng Shue ,  Kun-Ming Huang ,  Tzu-Cheng Chen ,  Ming-Che Yang ,  Po-Tao Chu

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7802 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/8238 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0634

Abstract: A method for forming a semiconductor device includes forming a hard mask layer over a substrate comprising a semiconductor material of a first conductivity type, and forming a plurality of trenches in the hard mask layer and extending into the substrate. Each trench has at least one side wall and a bottom wall. The method further includes forming at least one barrier insulator layer along the at least one side wall and over the bottom wall of each trench, removing the at least one barrier insulator layer over the bottom wall of each trench, and filling the plurality of trenches with a semiconductor material of a second conductivity type.

Abstract translation: 一种形成半导体器件的方法包括在包括第一导电类型的半导体材料的衬底上形成硬掩模层，并且在硬掩模层中形成并延伸到衬底中的多个沟槽。 每个沟槽具有至少一个侧壁和底壁。 该方法还包括沿着每个沟槽的至少一个侧壁和底壁上形成至少一个阻挡绝缘体层，在每个沟槽的底壁上去除至少一个阻挡绝缘体层，并且将多个沟槽填充到 第二导电类型的半导体材料。

公开(公告)号：US08779555B2

公开(公告)日：2014-07-15

申请号：US13706975

申请日：2012-12-06

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Long-Shih Lin ,  Fu-Hsiung Yang ,  Kun-Ming Huang ,  Ming-Yi Lin ,  Po-Tao Chu

IPC: H01L29/739 ,  H01L29/34

CPC classification number: H01L29/7824 ,  H01L21/6835 ,  H01L21/76202 ,  H01L21/76256 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/086 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66689 ,  H01L29/7394 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a method and apparatus to increase breakdown voltage of a semiconductor power device. A bonded wafer is formed by bonding a device wafer to a handle wafer with an intermediate oxide layer. The device wafer is thinned substantially from its original thickness. A power device is formed within the device wafer through a semiconductor fabrication process. The handle wafer is patterned to remove section of the handle wafer below the power device, resulting in a breakdown voltage improvement for the power device as well as a uniform electrostatic potential under reverse biasing conditions of the power device, wherein the breakdown voltage is determined. Other methods and structures are also disclosed.

Abstract translation: 本公开涉及一种增加半导体功率器件的击穿电压的方法和装置。 通过将器件晶片与具有中间氧化物层的手柄晶片结合来形成键合晶片。 器件晶片基本上从其原始厚度变薄。 通过半导体制造工艺在器件晶片内形成功率器件。 将处理晶片图案化以去除功率器件下方的处理晶片的部分，导致功率器件的击穿电压改善以及在功率器件的反向偏置条件下的均匀静电电势，其中确定击穿电压。 还公开了其它方法和结构。