公开(公告)号：US11189510B2

公开(公告)日：2021-11-30

申请号：US16655503

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yuan Chen ,  Hung-Jen Lu ,  Ming-Hsien Lee ,  Po-Tao Chu

IPC: H01L21/673

Abstract: The present disclosure, in some embodiments, relates to a method of transporting a semiconductor wafer. The method includes transferring a semiconductor wafer into a first wafer slot of a second plurality of wafer slots within an adaptive inset. The adaptive inset is arranged within an interior cavity of a wafer cassette having a first plurality of wafer slots while transferring the semiconductor wafer into the first wafer slot. The wafer cassette and the adaptive inset are transported into a loading port of a semiconductor processing tool configured to perform a fabrication process on the semiconductor wafer.

公开(公告)号：US11114543B2

公开(公告)日：2021-09-07

申请号：US15460582

申请日：2017-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hong Chang ,  Chih-Yuan Chan ,  Shen-Ping Wang ,  Chung-Cheng Chen ,  Chien-Li Kuo ,  Po-Tao Chu

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/778 ,  H01L21/768 ,  H01L21/74 ,  H01L29/423 ,  H01L23/31 ,  H01L23/532 ,  H01L23/522 ,  H01L29/20

Abstract: A group III-V device structure is provided. The group III-V device structure includes a channel layer formed over a substrate and an active layer formed over the channel layer. The group III-V device structure also includes a gate structure formed over the active layer and a source electrode and a drain electrode formed over the active layer. The source electrode and the drain electrode are formed on opposite sides of the gate structure. The group III-V device structure further includes a through via structure formed through the channel layer, the active layer and a portion of the substrate, and the through via structure is electrically connected to the source electrode or the drain electrode.

公开(公告)号：US10804231B2

公开(公告)日：2020-10-13

申请号：US16419280

申请日：2019-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hong Chang ,  Chun-Yi Yang ,  Kun-Ming Huang ,  Po-Tao Chu ,  Shen-Ping Wang ,  Chien-Li Kuo

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L23/50 ,  H01L23/29

Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

公开(公告)号：US20190273059A1

公开(公告)日：2019-09-05

申请号：US16419280

申请日：2019-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hong Chang ,  Chun-Yi Yang ,  Kun-Ming Huang ,  Po-Tao Chu ,  Shen-Ping Wang ,  Chien-Li Kuo

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L23/522

Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

公开(公告)号：US20190019770A1

公开(公告)日：2019-01-17

申请号：US15883797

申请日：2018-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hong Chang ,  Chun-Yi Yang ,  Kun-Ming Huang ,  Po-Tao Chu ,  Shen-Ping Wang ,  Chien-Li Kuo

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L23/522

Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

公开(公告)号：US20160087034A1

公开(公告)日：2016-03-24

申请号：US14494793

申请日：2014-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jheng-Sheng You ,  Che-Yi Lin ,  Shen-Ping Wang ,  Lieh-Chuan Chen ,  Po-Tao Chu

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7811 ,  H01L29/0634 ,  H01L29/0696

Abstract: The present disclosure relates to an integrated circuit with a termination region, and an associated method of formation. In some embodiments, the integrated circuit comprises a cell region and a termination region. The termination region is disposed at an outer periphery of the cell region. The cell region comprises an array of device cells. The termination region comprises a plurality of termination rings encompassing the cell region. The plurality of termination rings have different depths.

Abstract translation: 本公开涉及具有终端区域的集成电路及其相关联的形成方法。 在一些实施例中，集成电路包括单元区域和终端区域。 端子区域设置在电池区域的外周。 单元区域包括器件单元的阵列。 终端区域包括包围小区区域的多个终端环。 多个端接环具有不同的深度。

公开(公告)号：US20140264559A1

公开(公告)日：2014-09-18

申请号：US13866102

申请日：2013-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Hong-Seng Shue ,  Kun-Ming Huang ,  Tzu-Cheng Chen ,  Ming-Che Yang ,  Po-Tao Chu

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7802 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/8238 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0634

Abstract: A method for forming a semiconductor device includes forming a hard mask layer over a substrate comprising a semiconductor material of a first conductivity type, and forming a plurality of trenches in the hard mask layer and extending into the substrate. Each trench has at least one side wall and a bottom wall. The method further includes forming at least one barrier insulator layer along the at least one side wall and over the bottom wall of each trench, removing the at least one barrier insulator layer over the bottom wall of each trench, and filling the plurality of trenches with a semiconductor material of a second conductivity type.

Abstract translation: 一种形成半导体器件的方法包括在包括第一导电类型的半导体材料的衬底上形成硬掩模层，并且在硬掩模层中形成并延伸到衬底中的多个沟槽。 每个沟槽具有至少一个侧壁和底壁。 该方法还包括沿着每个沟槽的至少一个侧壁和底壁上形成至少一个阻挡绝缘体层，在每个沟槽的底壁上去除至少一个阻挡绝缘体层，并且将多个沟槽填充到 第二导电类型的半导体材料。

公开(公告)号：US08779555B2

公开(公告)日：2014-07-15

申请号：US13706975

申请日：2012-12-06

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Long-Shih Lin ,  Fu-Hsiung Yang ,  Kun-Ming Huang ,  Ming-Yi Lin ,  Po-Tao Chu

IPC: H01L29/739 ,  H01L29/34

CPC classification number: H01L29/7824 ,  H01L21/6835 ,  H01L21/76202 ,  H01L21/76256 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/086 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66689 ,  H01L29/7394 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a method and apparatus to increase breakdown voltage of a semiconductor power device. A bonded wafer is formed by bonding a device wafer to a handle wafer with an intermediate oxide layer. The device wafer is thinned substantially from its original thickness. A power device is formed within the device wafer through a semiconductor fabrication process. The handle wafer is patterned to remove section of the handle wafer below the power device, resulting in a breakdown voltage improvement for the power device as well as a uniform electrostatic potential under reverse biasing conditions of the power device, wherein the breakdown voltage is determined. Other methods and structures are also disclosed.

Abstract translation: 本公开涉及一种增加半导体功率器件的击穿电压的方法和装置。 通过将器件晶片与具有中间氧化物层的手柄晶片结合来形成键合晶片。 器件晶片基本上从其原始厚度变薄。 通过半导体制造工艺在器件晶片内形成功率器件。 将处理晶片图案化以去除功率器件下方的处理晶片的部分，导致功率器件的击穿电压改善以及在功率器件的反向偏置条件下的均匀静电电势，其中确定击穿电压。 还公开了其它方法和结构。

公开(公告)号：US20200051843A1

公开(公告)日：2020-02-13

申请号：US16655539

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yuan Chen ,  Hung-Jen Lu ,  Ming-Hsien Lee ,  Po-Tao Chu

IPC: H01L21/673

Abstract: The present disclosure, in some embodiments, relates to a wafer cassette system. The wafer cassette system includes a wafer cassette includes a first plurality of wafer slots respectively having a first width. An adaptive inset is fastened to the wafer cassette in a rigid connection. The adaptive inset includes a second plurality of wafer slots respectively having a second width that is less than the first width. The second plurality of wafer slots are configured to receive a substrate after the adaptive inset has been fastened to the wafer cassette.

公开(公告)号：US10535541B2

公开(公告)日：2020-01-14

申请号：US15288155

申请日：2016-10-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yuan Chen ,  Hung-Jen Lu ,  Ming-Hsien Lee ,  Po-Tao Chu

IPC: B65G29/00 ,  H01L21/673

Abstract: The present disclosure relates to a wafer cassette system having an adaptive inset configured to enable wafers having a first diameter to be held by a wafer cassette configured to hold wafers having a second diameter larger than the first diameter. The wafer cassette system includes a wafer cassette having a first plurality of wafer slots configured to receive one or more wafers having a first diameter. An adaptive inset is arranged in an interior cavity of the wafer cassette. The adaptive inset has a second plurality of wafer slots configured to receive one or more wafers having a second diameter that is less than the first diameter. The adaptive inset allows for the wafer cassette to hold wafers having the second diameter, thereby enabling semiconductor processing tools to processes wafer having a different diameter than those able to be held by wafer cassettes that the tools can receive.