公开(公告)号：US09698256B2

公开(公告)日：2017-07-04

申请号：US14494793

申请日：2014-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jheng-Sheng You ,  Che-Yi Lin ,  Shen-Ping Wang ,  Lieh-Chuan Chen ,  Po-Tao Chu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7811 ,  H01L29/0634 ,  H01L29/0696

Abstract: The present disclosure relates to an integrated circuit with a termination region, and an associated method of formation. In some embodiments, the integrated circuit comprises a cell region and a termination region. The termination region is disposed at an outer periphery of the cell region. The cell region comprises an array of device cells. The termination region comprises a plurality of termination rings encompassing the cell region. The plurality of termination rings have different depths.

公开(公告)号：US09564515B2

公开(公告)日：2017-02-07

申请号：US14444861

申请日：2014-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jheng-Sheng You ,  Che-Yi Lin ,  Shen-Ping Wang ,  Kun-Ming Huang ,  Lieh-Chuan Chen ,  Po-Tao Chu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/66712 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/7802

Abstract: A semiconductor device having a super junction structure includes a substrate, an epitaxial layer of a first conductivity type, a first trench, a first doped region of a second conductivity type opposite to the first conductivity type, a second trench and a second doped region of the first conductivity type. The epitaxial layer of the first conductivity type is over the substrate. The first trench is in the epitaxial layer. The first doped region of the second conductivity type is in the epitaxial layer and surrounds the first trench. The second trench is in the epitaxial layer and separated from the first trench. The second doped region of the first conductivity type is in the epitaxial layer and surrounds the second trench. The second doped region has a dopant concentration greater than a dopant concentration of the epitaxial layer. A method for manufacturing the semiconductor device is also provided.

Abstract translation: 具有超结结构的半导体器件包括衬底，第一导电类型的外延层，第一沟槽，与第一导电类型相反的第二导电类型的第一掺杂区，第二沟槽和第二掺杂区 第一种导电类型。 第一导电类型的外延层在衬底上。 第一沟槽在外延层中。 第二导电类型的第一掺杂区域在外延层中并围绕第一沟槽。 第二沟槽在外延层中并与第一沟槽分离。 第一导电类型的第二掺杂区域在外延层中并且包围第二沟槽。 第二掺杂区域的掺杂浓度大于外延层的掺杂剂浓度。 还提供了一种用于制造半导体器件的方法。

公开(公告)号：US20160087034A1

公开(公告)日：2016-03-24

申请号：US14494793

申请日：2014-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jheng-Sheng You ,  Che-Yi Lin ,  Shen-Ping Wang ,  Lieh-Chuan Chen ,  Po-Tao Chu

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7811 ,  H01L29/0634 ,  H01L29/0696

Abstract: The present disclosure relates to an integrated circuit with a termination region, and an associated method of formation. In some embodiments, the integrated circuit comprises a cell region and a termination region. The termination region is disposed at an outer periphery of the cell region. The cell region comprises an array of device cells. The termination region comprises a plurality of termination rings encompassing the cell region. The plurality of termination rings have different depths.

Abstract translation: 本公开涉及具有终端区域的集成电路及其相关联的形成方法。 在一些实施例中，集成电路包括单元区域和终端区域。 端子区域设置在电池区域的外周。 单元区域包括器件单元的阵列。 终端区域包括包围小区区域的多个终端环。 多个端接环具有不同的深度。