公开(公告)号：US20180059992A1

公开(公告)日：2018-03-01

申请号：US15489196

申请日：2017-04-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jean-Pierre COLINGE ,  Carlos H. DIAZ ,  Ta-Pen GUO

IPC: G06F3/06 ,  H01L27/11514 ,  G11C13/02 ,  G11C15/04 ,  G11C14/00

CPC classification number: G06F3/0679 ,  B82Y10/00 ,  G06F3/0688 ,  G11C13/025 ,  G11C14/0018 ,  G11C14/009 ,  G11C15/046 ,  H01L21/02491 ,  H01L27/0688 ,  H01L27/11514 ,  H01L27/11578 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66833 ,  H01L29/775 ,  H01L29/78654 ,  H01L29/78696 ,  H01L29/792

Abstract: Semiconductor structures and methods for crystalline junctionless transistors used in nonvolatile memory arrays are introduced. Various embodiments in accordance with this disclosure provide a method of fabricating a monolithic 3D cross-bar nonvolatile memory array with low thermal budget. The method incorporates crystalline junctionless transistors into nonvolatile memory structures by transferring a layer of doped crystalline semiconductor material from a seed wafer to form the source, drain, and connecting channel of the junctionless transistor.

公开(公告)号：US20170256696A1

公开(公告)日：2017-09-07

申请号：US15057734

申请日：2016-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre COLINGE ,  Yu-Ming LIN

IPC: H01L35/32

CPC classification number: H01L35/325

Abstract: Thermoelectric generators are provided. A thermoelectric generator includes a thermoelectric structure and a rectifier bridge. The thermoelectric structure includes a semiconductor substrate, a first metal layer disposed on the semiconductor substrate, a dielectric layer disposed on the first metal layer, a second metal layer disposed on the dielectric layer, and a plurality of first materials disposed in the dielectric layer and coupled between the first electrodes and the second electrodes. The first metal layer includes a plurality of first electrodes. The second metal layer includes a plurality of second electrodes. The rectifier bridge coupled to the thermoelectric structure provides an output voltage according to electrical energy from the thermoelectric structure. The thermoelectric structure provides the electrical energy according to a temperature difference between the first metal layer and the second metal layer. The first material is a thermoelectric material.

公开(公告)号：US20170221717A1

公开(公告)日：2017-08-03

申请号：US15485340

申请日：2017-04-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jean-Pierre COLINGE ,  Carlos H. DIAZ

IPC: H01L21/285 ,  H01L29/45 ,  H01L21/02 ,  H01L29/78 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L21/28518 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/30604 ,  H01L21/465 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a fin structure disposed over a substrate, a gate structure and a source. The fin structure includes an upper layer being exposed from an isolation insulating layer. The gate structure disposed over part of the upper layer of the fin structure. The source includes the upper layer of the fin structure not covered by the gate structure. The upper layer of the fin structure of the source is covered by a crystal semiconductor layer. The crystal semiconductor layer is covered by a silicide layer formed by Si and a first metal element. The silicide layer is covered by a first metal layer. A second metal layer made of the first metal element is disposed between the first metal layer and the isolation insulating layer.

公开(公告)号：US20170221555A1

公开(公告)日：2017-08-03

申请号：US15487526

申请日：2017-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Carlos H. DIAZ ,  Chih-Hao WANG ,  Jean-Pierre COLINGE ,  Ta-Pen GUO

IPC: G11C11/419 ,  G11C11/412

Abstract: Static random access memories (SRAM) are provided. The SRAM includes a plurality of bit cells. Each bit cell includes a first inverter, a second inverter cross-coupled with the first inverter, a first pass gate transistor coupled between the first inverter and a bit line, and a second pass gate transistor coupled between the second inverter and a complementary bit line. The bit cells are divided into a plurality of top tier cells and a plurality of bottom tier cells, and each of the bottom tier cells is disposed under the individual top tier cell. The first inverter of the top tier cell is disposed on the second inverter of the corresponding bottom tier cell within a substrate, and the second inverter of the top tier cell is disposed on the first inverter of the corresponding bottom tier cell within the substrate.

公开(公告)号：US20170110180A1

公开(公告)日：2017-04-20

申请号：US14918068

申请日：2015-10-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Ta-Pen GUO ,  Carlos H. DIAZ ,  Chih-Hao WANG ,  Jean-Pierre COLINGE

IPC: G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412 ,  H01L27/11582 ,  H01L28/00

Abstract: Static random access memories (SRAM) are provided. The SRAM includes a plurality of bit cells. Each bit cell includes a first inverter, a second inverter cross-coupled with the first inverter, a first pass gate transistor coupled between the first inverter and a bit line, and a second pass gate transistor coupled between the second inverter and a complementary bit line. The bit cells are divided into a plurality of top tier cells and a plurality of bottom tier cells, and each of the bottom tier cells is disposed under the individual top tier cell. The first inverter of the top tier cell is disposed on the second inverter of the corresponding bottom tier cell within a substrate, and the second inverter of the top tier cell is disposed on the first inverter of the corresponding bottom tier cell within the substrate.

公开(公告)号：US20160343857A1

公开(公告)日：2016-11-24

申请号：US14720721

申请日：2015-05-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jean-Pierre COLINGE ,  Carlos H. DIAZ

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/45 ,  H01L21/306 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7845 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02667 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of manufacturing a Fin FET includes forming a fin structure over a substrate. The fin structure includes an upper layer, and part of the upper layer is exposed from an isolation insulating layer. A gate structure is formed over part of the fin structure. An amorphous layer is formed over the gate structure and the fin structure not covered by the gate structure. A recrystallized layer is formed by partially recrystallizing the amorphous layer over the fin structure not covered by the gate structure. A remaining amorphous layer which is not recrystallized is removed. Source and drain electrode layers are formed over the recrystallized layer.

Abstract translation: 制造Fin FET的方法包括在衬底上形成翅片结构。 翅片结构包括上层，并且上层的一部分从隔离绝缘层露出。 栅极结构形成在鳍结构的一部分上。 在栅极结构上形成非晶层，并且鳍状结构未被栅极结构覆盖。 通过在未被栅极结构覆盖的鳍结构上的非晶层部分重结晶来形成再结晶层。 除去未再结晶的剩余非晶层。 源极和漏极电极层形成在再结晶层上。

公开(公告)号：US20200052120A1

公开(公告)日：2020-02-13

申请号：US16595580

申请日：2019-10-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre COLINGE ,  Carlos H. DIAZ

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/265 ,  H01L21/02 ,  H01L29/165 ,  H01L29/417

Abstract: Semiconductor structures and methods reduce contact resistance, while retaining cost effectiveness for integration into the process flow by introducing a heavily-doped contact layer disposed between two adjacent layers. The heavily-doped contact layer may be formed through a solid-phase epitaxial regrowth method. The contact resistance may be tuned by adjusting dopant concentration and contact area configuration of the heavily-doped epitaxial contact layer.

公开(公告)号：US20190097147A1

公开(公告)日：2019-03-28

申请号：US16201742

申请日：2018-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh LU ,  Yu-Ming LIN ,  Ken-Ichi GOTO ,  Jean-Pierre COLINGE ,  Zhiqiang Wu

IPC: H01L51/05 ,  H01L51/00 ,  H01L51/10

Abstract: In a method of manufacturing a gate-all-around field effect transistor, a trench is formed over a substrate. Nano-tube structures are arranged into the trench, each of which includes a carbon nanotube (CNT) having a gate dielectric layer wrapping around the CNT and a gate electrode layer over the gate dielectric layer. An anchor layer is formed in the trench. A part of the anchor layer is removed at a source/drain (S/D) region. The gate electrode layer and the gate dielectric layer are removed at the S/D region, thereby exposing a part of the CNT at the S/D region. An S/D electrode layer is formed on the exposed part of the CNT. A part of the anchor layer is removed at a gate region, thereby exposing a part of the gate electrode layer of the gate structure. A gate contact layer is formed on the exposed part of the gate electrode layer.

公开(公告)号：US20180166575A1

公开(公告)日：2018-06-14

申请号：US15893316

申请日：2018-02-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre COLINGE ,  Carlos H. DIAZ

IPC: H01L29/78

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02592 ,  H01L21/02636 ,  H01L21/02667 ,  H01L21/26513 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: Semiconductor structures and methods reduce contact resistance, while retaining cost effectiveness for integration into the process flow by introducing a heavily-doped contact layer disposed between two adjacent layers. The heavily-doped contact layer may be formed through a solid-phase epitaxial regrowth method. The contact resistance may be tuned by adjusting dopant concentration and contact area configuration of the heavily-doped epitaxial contact layer.

公开(公告)号：US20170338237A1

公开(公告)日：2017-11-23

申请号：US15196126

申请日：2016-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jean-Pierre COLINGE ,  Carlos H. Diaz

IPC: H01L27/11568 ,  H01L29/423 ,  H01L21/28 ,  H01L21/02 ,  H01L27/12 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of fabricating nanocrystal memory array includes stacking a silicon layer and a silicon germanium layer on a wafer. A gate oxide layer over is then formed on the silicon layer and the silicon germanium layer. Next, a gate layer is deposited on the gate oxide layer. Subsequently, the gate layer, gate oxide layer and the silicon germanium layer are patterned. Finally, the silicon germanium layer is oxidized. The nanocrystal is sandwiched in between the gate and the silicon layer, and the gate oxide layer surrounds the nanocrystal.