公开(公告)号：US20240096961A1

公开(公告)日：2024-03-21

申请号：US18520996

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chuan CHIU ,  Tien-Lu LIN ,  Yu-Ming LIN ,  Chia-Hao CHANG ,  Chih-Hao WANG ,  Jia-Chuan YOU

IPC: H01L29/08 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/76871 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A contact stack of a semiconductor device includes a source/drain feature, a silicide layer wrapping around the source/drain feature, a seed metal layer in direct contact with the silicide layer, and a conductor in contact with the seed metal layer. The contact stack excludes a metal nitride layer in direct contact with the silicide layer.

公开(公告)号：US20230275156A1

公开(公告)日：2023-08-31

申请号：US18295198

申请日：2023-04-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan YOU ,  Chia-Hao CHANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L21/28 ,  H01L21/321 ,  H01L21/768 ,  H01L29/417

CPC classification number: H01L29/7851 ,  H01L21/3212 ,  H01L21/28088 ,  H01L21/76829 ,  H01L29/4966 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/511

Abstract: A method includes a gate structure, gate spacers, a gate helmet, a metal cap, and a gate contact. The gate structure is over a substrate. The gate spacers are on either side of the gate structure. The gate helmet is over the gate structure and the gate spacers. The metal cap is in the gate helmet over the gate structure. The gate contact is over the metal cap. The gate contact forms an interface with the metal cap at a different level height than top segments of the gate spacers.

公开(公告)号：US20220293459A1

公开(公告)日：2022-09-15

申请号：US17830994

申请日：2022-06-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan YOU ,  Chia-Hao CHANG ,  Wai-Yi LIEN ,  Yu-Ming LIN

IPC: H01L21/768 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/28 ,  H01L23/485 ,  H01L29/417

Abstract: A method includes forming a gate stack over a substrate and a gate spacer on a sidewall of the gate stack; forming a source/drain region in the substrate and adjacent to the gate spacer; forming a first interlayer dielectric layer over the source/drain region; forming a protective layer over the gate stack and in contact with a top surface of the gate spacer; removing the first interlayer dielectric layer after forming the protective layer; forming an etch stop layer over the protective layer; forming a second interlayer dielectric layer over the etch stop layer; etching the second interlayer dielectric layer and the etch stop layer to form an opening that exposes a top surface of the protective layer; and forming a contact plug in the opening.

公开(公告)号：US20210265218A1

公开(公告)日：2021-08-26

申请号：US16800246

申请日：2020-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Lin CHUANG ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L21/768

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first gate structure and a second gate structure formed over a semiconductor substrate. The semiconductor device structure also includes a first insulating cap structure formed between and adjacent to the first gate structure and the second gate structure. The first insulating cap structure is separated from the semiconductor substrate by a first air gap. The first air gap includes a first portion extending into the first insulating cap structure and a second portion extended from the bottom of the first portion toward the semiconductor substrate. The first portion has a width that is less than the width of the second portion.

公开(公告)号：US20210083046A1

公开(公告)日：2021-03-18

申请号：US16572192

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tien-Lu LIN ,  Che-Chen WU ,  Chia-Lin CHUANG ,  Yu-Ming LIN ,  Chih-Hao CHANG

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/764

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain contact structure formed over a semiconductor substrate, and a first gate stack formed over the semiconductor substrate and adjacent to the source/drain contact structure. The semiconductor device structure also includes an insulating cap structure formed over and separated from an upper surface of the first gate stack. In addition, the semiconductor device structure includes first gate spacers formed over opposing sidewalls of the first gate stack to separate the first gate stack from the source/drain contact structure. The first gate spacers extend over opposing sidewalls of the insulating cap structure, so as to form an air gap surrounded by the first gate spacers, the first gate stack, and the insulating cap structure.

公开(公告)号：US20200303259A1

公开(公告)日：2020-09-24

申请号：US16897229

申请日：2020-06-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yasutoshi OKUNO ,  Cheng-Yi PENG ,  Ziwei FANG ,  I-Ming CHANG ,  Akira MINEJI ,  Yu-Ming LIN ,  Meng-Hsuan HSIAO

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/203 ,  H01L27/092 ,  H01L21/8238

Abstract: A method of forming a semiconductor device including a fin field effect transistor (FinFET), the method includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer made of Si1-y-a-bGeaSnbM2y, wherein 0

公开(公告)号：US20200294846A1

公开(公告)日：2020-09-17

申请号：US16353421

申请日：2019-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu HUANG ,  Jia-Chuan YOU ,  Chia-Hao CHANG ,  Tien-Lu LIN ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78

Abstract: A method for forming a fin field effect transistor device structure includes forming fin structures over a substrate. The method also includes forming a gate structure across the fin structures. The method also includes forming source/drain epitaxial structures over the fin structures. The method also includes forming blocking structures between the source/drain epitaxial structures. The method also includes depositing contact structures over the source/drain epitaxial structures and between the blocking structures. The method also includes removing a top portion of the blocking structures. The method also includes depositing an etch stop layer over the blocking structures and the contact structures, so that an air gap is formed between the etch stop layer and the blocking structure.

公开(公告)号：US20200243519A1

公开(公告)日：2020-07-30

申请号：US16257375

申请日：2019-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen YU ,  Tien-Lu LIN ,  Jia-Chuan YOU ,  Chia-Hao CHANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/033 ,  H01L21/8234

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first epitaxial structure and a second epitaxial structure over a semiconductor substrate. The method includes forming a dielectric layer over the first epitaxial structure, the second epitaxial structure, and the semiconductor substrate. The method includes forming a first mask layer over the dielectric layer and between the first epitaxial structure and the second epitaxial structure. The method includes forming a second mask layer over the dielectric layer and the first mask layer. The method includes partially removing the dielectric layer covering the first epitaxial structure and the second epitaxial structure. The method includes removing the first mask layer. The method includes forming a first conductive layer and a second conductive layer respectively in the first recess and the second recess.

公开(公告)号：US20200035558A1

公开(公告)日：2020-01-30

申请号：US16422559

申请日：2019-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Lin-Yu HUANG ,  Huan-Chieh SU ,  Sheng-Tsung WANG ,  Zhi-Chang LIN ,  Jia-Chuan YOU ,  Chia-Hao CHANG ,  Tien-Lu LIN ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L21/768 ,  H01L21/28 ,  H01L29/40 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes providing a device having a gate stack including a metal gate layer. The device further includes a spacer layer disposed on a sidewall of the gate stack and a source/drain feature adjacent to the gate stack. The method further includes performing a first etch-back process to the metal gate layer to form an etched-back metal gate layer. In some embodiments, the method includes depositing a metal layer over the etched-back metal gate layer. In some cases, a semiconductor layer is formed over both the metal layer and the spacer layer to provide a T-shaped helmet layer over the gate stack and the spacer layer.

公开(公告)号：US20190096759A1

公开(公告)日：2019-03-28

申请号：US15719395

申请日：2017-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hao CHANG ,  Jia-Chuan YOU ,  Yu-Ming LIN ,  Chih-Hao WANG ,  Wai-Yi LIEN

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/528

Abstract: A method of forming a semiconductor device includes forming an ILD structure over a source/drain region, forming a source/drain contact in the ILD structure and over the source/drain region, removing a portion of the source/drain contact such that a hole is formed in the ILD structure and over a remaining portion of the source/drain contact, forming a hole liner lining a sidewall of the hole, and forming a conductive structure in the hole.