公开(公告)号：US09711607B1

公开(公告)日：2017-07-18

申请号：US15130527

申请日：2016-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd. ,  National Taiwan University

Inventor： Che-Wei Yang ,  Chi-Wen Liu ,  Hao-Hsiung Lin ,  Ling-Yen Yeh

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L27/12 ,  H01L21/20 ,  H01L21/02

CPC classification number: H01L29/42392 ,  H01L21/02444 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/02645 ,  H01L21/2018 ,  H01L27/1281 ,  H01L29/0673 ,  H01L29/66469 ,  H01L29/66477 ,  H01L29/775 ,  H01L29/78

Abstract: A method and structure for providing a GAA device. In some embodiments, a substrate including an insulating layer disposed thereon is provided. By way of example, a first metal portion is formed within the insulating layer. In various embodiments, a first lateral surface of the first metal portion is exposed. After exposure of the first lateral surface of the first metal portion, a first graphene layer is formed on the exposed first lateral surface. In some embodiments, the first graphene layer defines a first vertical plane parallel to the exposed first lateral surface. Thereafter, in some embodiments, a first nanobar is formed on the first graphene layer, where the first nanobar extends in a first direction normal to the first vertical plane defined by the first graphene layer.

公开(公告)号：US20170069757A1

公开(公告)日：2017-03-09

申请号：US14994057

申请日：2016-01-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Ming Peng ,  Chi-Wen Liu ,  Hsin-Chieh Huang ,  Yi-Ju Hsu ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.

Abstract translation: FinFET器件包括衬底，形成在衬底上的鳍片和与鳍片交叉的栅极电极。 栅电极包括头部和尾部，尾部连接到头部并朝向衬底延伸。 头部的宽度大于尾部的宽度。

公开(公告)号：US20170069621A1

公开(公告)日：2017-03-09

申请号：US14990603

申请日：2016-01-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Chien Huang ,  Chi-Wen Liu ,  Horng-Huei Tseng ,  Tsung-Yu Chiang

IPC: H01L27/06 ,  H01L29/06 ,  H01L49/02 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762 ,  H01L29/78 ,  H01L23/528

CPC classification number: H01L27/0629 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/528 ,  H01L28/24 ,  H01L29/0611 ,  H01L29/0653 ,  H01L29/42364 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.

Abstract translation: 半导体器件包括FinFET部件，布置在FinFET部件的多个鳍片上的多个图案化虚拟半导体鳍片，形成在图案化虚拟半导体鳍片上的隔离结构以及形成在图案化虚拟半导体鳍片上的调谐组件， 连接到FinFET组件。 图案化虚拟半导体鳍片的高度比FinFET部件的鳍片的高度短。

公开(公告)号：US20140339631A1

公开(公告)日：2014-11-20

申请号：US14450809

申请日：2014-08-04

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Yu-Wei Ting ,  Chi-Wen Liu ,  Chun-Yang Tsai ,  Kuo-Ching Huang

IPC: H01L29/78 ,  H01L27/24 ,  H01L27/22 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L27/2454 ,  H01L27/228 ,  H01L27/2463 ,  H01L29/4236 ,  H01L29/7827

Abstract: Some embodiments of the present disclosure relate to a memory array comprising memory cells having vertical gate-all-around (GAA) selection transistors. In some embodiments, the memory array has a source region disposed within an upper surface of a semiconductor body, and a semiconductor pillar of semiconductor material extending outward from the upper surface of the semiconductor body and having a channel region and an overlying drain region. A gate region vertically overlies the source region at a position laterally separated from sidewalls of the channel region by a gate dielectric layer. A first metal contact couples the drain region to a data storage element that stores data. The vertical GAA selection transistors provide for good performance, while decreasing the size of the selection transistor relative to a planar MOSFET, so that the selection transistors do not negatively impact the size of the memory array.

Abstract translation: 本公开的一些实施例涉及包括具有垂直栅极全周（GAA）选择晶体管的存储器单元的存储器阵列。 在一些实施例中，存储器阵列具有设置在半导体本体的上表面内的源极区域和从半导体本体的上表面向外延伸并具有沟道区域和上覆漏极区域的半导体材料的半导体柱。 栅极区域通过栅极介电层在与沟道区域的侧壁横向分离的位置处垂直地覆盖源极区域。 第一金属触点将漏极区域耦合到存储数据的数据存储元件。 垂直GAA选择晶体管提供良好的性能，同时相对于平面MOSFET减小选择晶体管的尺寸，使得选择晶体管不会对存储器阵列的尺寸产生负面影响。

公开(公告)号：US11682625B2

公开(公告)日：2023-06-20

申请号：US17359083

申请日：2021-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Chi-Wen Liu ,  Horng-Huei Tseng

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/535 ,  H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L29/66 ,  H01L29/417 ,  H01L27/092 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/45 ,  H01L23/485

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/823821 ,  H01L23/53266 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/78696 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/458 ,  H01L29/66545

Abstract: A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.

公开(公告)号：US11437479B2

公开(公告)日：2022-09-06

申请号：US16883227

申请日：2020-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Chi-Wen Liu ,  Ying-Keung Leung

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/108 ,  H01L27/12 ,  H01L27/088 ,  H01L29/06 ,  H01L29/45

Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.

公开(公告)号：US11205594B2

公开(公告)日：2021-12-21

申请号：US16895345

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Ting-Hung Hsu ,  Chao-Hsiung Wang ,  Chi-Wen Liu

IPC: H01L29/165 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/762

Abstract: A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin.

公开(公告)号：US20210280575A1

公开(公告)日：2021-09-09

申请号：US17327071

申请日：2021-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chien Huang ,  Chi-Wen Liu ,  Horng-Huei Tseng ,  Tsung-Yu Chiang

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/06 ,  H01L49/02 ,  H01L23/528 ,  H01L29/423 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088

Abstract: A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.

公开(公告)号：US10741646B2

公开(公告)日：2020-08-11

申请号：US16404289

申请日：2019-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ling-Yen Yeh ,  Yee-Chia Yeo ,  Chi-Wen Liu

IPC: H01L29/10 ,  H01L29/778 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/24 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78

Abstract: Exemplary FET devices having 2D material layer active regions and methods of fabricating thereof are described. For example, a black phosphorus active region has a first thickness in the channel region and a second, greater, thickness in the source/drain (S/D) region. The BP in the S/D region has a sidewall that interfaces a contact disposed over the FET. A gate electrode is disposed over the channel region. In some embodiments, the sidewall has passivated edge. In some embodiments, the sidewall is nonlinear. In some embodiments, the stress layer is disposed over the 2D material layer.

公开(公告)号：US20190279939A1

公开(公告)日：2019-09-12

申请号：US16416454

申请日：2019-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Chi-Wen Liu ,  Horng-Huei Tseng

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/535 ,  H01L27/12 ,  H01L27/092 ,  H01L29/78 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/417 ,  H01L23/485 ,  H01L21/285 ,  H01L21/3065 ,  H01L23/528

Abstract: A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions is present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of a interconnection structure in the semiconductor device is reduced.