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    High electron affinity dielectric layer to improve cycling
    1.
    发明授权
    High electron affinity dielectric layer to improve cycling 有权

    公开(公告)号：US11696521B2

    公开(公告)日：2023-07-04

    申请号：US16939497

    申请日：2020-07-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-Yang Chen ,  Chun-Yang Tsai ,  Kuo-Ching Huang ,  Wen-Ting Chu ,  Cheng-Jun Wu

    IPC: H01L45/00 ,  H10N70/00 ,  G11C13/00 ,  H10B63/00

    CPC classification number: H10N70/883 ,  G11C13/0007 ,  H10B63/00 ,  H10N70/021 ,  H10N70/841

    Abstract: Various embodiments of the present disclosure are directed towards a memory cell comprising a high electron affinity dielectric layer at a bottom electrode. The high electron affinity dielectric layer is one of multiple different dielectric layers vertically stacked between the bottom electrode and a top electrode overlying the bottom electrode. Further, the high electrode electron affinity dielectric layer has a highest electron affinity amongst the multiple different dielectric layers and is closest to the bottom electrode. The different dielectric layers are different in terms of material systems and/or material compositions. It has been appreciated that by arranging the high electron affinity dielectric layer closest to the bottom electrode, the likelihood of the memory cell becoming stuck during cycling is reduced at least when the memory cell is RRAM. Hence, the likelihood of a hard reset/failure bit is reduced.

    HIGH ELECTRON AFFINITY DIELECTRIC LAYER TO IMPROVE CYCLING
    2.
    发明申请
    HIGH ELECTRON AFFINITY DIELECTRIC LAYER TO IMPROVE CYCLING 有权

    公开(公告)号：US20210135105A1

    公开(公告)日：2021-05-06

    申请号：US16939497

    申请日：2020-07-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-Yang Chen ,  Chun-Yang Tsai ,  Kuo-Ching Huang ,  Wen-Ting Chu ,  Cheng-Jun Wu

    IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

    Abstract: Various embodiments of the present disclosure are directed towards a memory cell comprising a high electron affinity dielectric layer at a bottom electrode. The high electron affinity dielectric layer is one of multiple different dielectric layers vertically stacked between the bottom electrode and a top electrode overlying the bottom electrode. Further, the high electrode electron affinity dielectric layer has a highest electron affinity amongst the multiple different dielectric layers and is closest to the bottom electrode. The different dielectric layers are different in terms of material systems and/or material compositions. It has been appreciated that by arranging the high electron affinity dielectric layer closest to the bottom electrode, the likelihood of the memory cell becoming stuck during cycling is reduced at least when the memory cell is RRAM. Hence, the likelihood of a hard reset/failure bit is reduced.

    Multi-step reset technique to enlarge memory window
    3.
    发明授权
    Multi-step reset technique to enlarge memory window 有权

    公开(公告)号：US10861547B1

    公开(公告)日：2020-12-08

    申请号：US16417705

    申请日：2019-05-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-Yang Chen ,  Cheng-Jun Wu ,  Chun-Yang Tsai ,  Kuo-Ching Huang

    IPC: G11C11/00 ,  G11C13/00 ,  H01L45/00

    Abstract: In some embodiments, the present disclosure relates to a method of operation a resistive random access memory (RRAM) cell, comprising the performing of a reset operation to the RRAM cell. A first voltage bias is applied to the RRAM cell. The first voltage bias has a first polarity. The application of the first voltage bias induces the RRAM cell to change from a low resistance to an intermediate resistance. The intermediate resistance is greater than the low resistance. A second voltage bias is then applied to the RRAM cell. The second voltage bias has a second polarity that is opposite to the first polarity. The application of the second voltage bias induces the RRAM cell to have a high resistance. The high resistance is greater than the intermediate resistance.

    MULTI-STEP RESET TECHNIQUE TO ENLARGE MEMORY WINDOW
    4.
    发明申请
    MULTI-STEP RESET TECHNIQUE TO ENLARGE MEMORY WINDOW 审中-公开

    公开(公告)号：US20200372955A1

    公开(公告)日：2020-11-26

    申请号：US16417705

    申请日：2019-05-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-Yang Chen ,  Cheng-Jun Wu ,  Chun-Yang Tsai ,  Kuo-Ching Huang

    IPC: G11C13/00

    Abstract: In some embodiments, the present disclosure relates to a method of operation a resistive random access memory (RRAM) cell, comprising the performing of a reset operation to the RRAM cell. A first voltage bias is applied to the RRAM cell. The first voltage bias has a first polarity. The application of the first voltage bias induces the RRAM cell to change from a low resistance to an intermediate resistance. The intermediate resistance is greater than the low resistance. A second voltage bias is then applied to the RRAM cell. The second voltage bias has a second polarity that is opposite to the first polarity. The application of the second voltage bias induces the RRAM cell to have a high resistance. The high resistance is greater than the intermediate resistance.

    MEMORY CIRCUIT AND FORMATION METHOD THEREOF
    5.
    发明申请
    MEMORY CIRCUIT AND FORMATION METHOD THEREOF 审中-公开

    公开(公告)号：US20190058007A1

    公开(公告)日：2019-02-21

    申请号：US15678557

    申请日：2017-08-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Yang Tsai ,  Kuo-Ching Huang ,  Tong-Chern Ong

    IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

    Abstract: The present disclosure relates to a memory circuit having a shared control device for access to target and complementary memory devices for improved differential sensing. The memory circuit has a control device arranged within a substrate and having a first terminal coupled to a source-line, a second terminal coupled to a word-line, and a third terminal. A first memory device has a first lower electrode separated from a first upper electrode by a first data storage layer. The first upper electrode is coupled to the third terminal and the first lower electrode is coupled to a first bit-line. A second memory device has a second lower electrode separated from a second upper electrode by a second data storage layer. The second upper electrode is coupled to the second bit-line and the second lower electrode is coupled to the third terminal.

    Bottom electrode structure in memory device
    8.
    发明授权
    Bottom electrode structure in memory device 有权

    公开(公告)号：US11631810B2

    公开(公告)日：2023-04-18

    申请号：US17233755

    申请日：2021-04-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-Yang Chen ,  Chun-Yang Tsai ,  Kuo-Ching Huang ,  Wen-Ting Chu ,  Pili Huang ,  Cheng-Jun Wu

    IPC: H01L27/088 ,  H01L21/8236 ,  H01L45/00 ,  H01L27/24

    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes one or more lower interconnects arranged within a dielectric structure over a substrate. A bottom electrode is disposed over one of the one or more lower interconnects. The bottom electrode includes a first material having a first electronegativity. A data storage layer separates the bottom electrode from a top electrode. The bottom electrode is between the data storage layer and the substrate. A reactivity reducing layer includes a second material and has a second electronegativity that is greater than or equal to the first electronegativity. The second material contacts a lower surface of the bottom electrode that faces the substrate.

    MULTI-STEP RESET TECHNIQUE TO ENLARGE MEMORY WINDOW
    9.
    发明申请
    MULTI-STEP RESET TECHNIQUE TO ENLARGE MEMORY WINDOW 有权

    公开(公告)号：US20210043257A1

    公开(公告)日：2021-02-11

    申请号：US17082232

    申请日：2020-10-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-Yang Chen ,  Cheng-Jun Wu ,  Chun-Yang Tsai ,  Kuo-Ching Huang

    IPC: G11C13/00

    Abstract: In some embodiments, the present disclosure relates to a method, comprising the performing of a reset operation to a resistive random access memory (RRAM) cell. A first voltage bias having a first polarity is applied to the RRAM cell. An absolute value of the first voltage bias is greater than an absolute value of a first reset voltage. The application of the first voltage bias induces the RRAM cell to change from a low resistance to an intermediate resistance greater than the low resistance. A second voltage bias having a second polarity oppose to the first polarity is then applied to the RRAM cell. An absolute value of the second reset voltage is less than an absolute value of the second voltage bias and less than the absolute value of the first reset voltage. The application of the second voltage bias induces the RRAM cell to have a high resistance.

    Memory circuit and formation method thereof
    10.
    发明授权
    Memory circuit and formation method thereof 有权

    公开(公告)号：US10461126B2

    公开(公告)日：2019-10-29

    申请号：US15678557

    申请日：2017-08-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Yang Tsai ,  Kuo-Ching Huang ,  Tong-Chern Ong

    IPC: H01L29/788 ,  H01L21/336 ,  H01L27/24 ,  G11C13/00 ,  H01L45/00 ,  G11C11/16

    Abstract: The present disclosure relates to a memory circuit having a shared control device for access to target and complementary memory devices for improved differential sensing. The memory circuit has a control device arranged within a substrate and having a first terminal coupled to a source-line, a second terminal coupled to a word-line, and a third terminal. A first memory device has a first lower electrode separated from a first upper electrode by a first data storage layer. The first upper electrode is coupled to the third terminal and the first lower electrode is coupled to a first bit-line. A second memory device has a second lower electrode separated from a second upper electrode by a second data storage layer. The second upper electrode is coupled to the second bit-line and the second lower electrode is coupled to the third terminal.

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