公开(公告)号：US11631810B2

公开(公告)日：2023-04-18

申请号：US17233755

申请日：2021-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yang Chen ,  Chun-Yang Tsai ,  Kuo-Ching Huang ,  Wen-Ting Chu ,  Pili Huang ,  Cheng-Jun Wu

IPC: H01L27/088 ,  H01L21/8236 ,  H01L45/00 ,  H01L27/24

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes one or more lower interconnects arranged within a dielectric structure over a substrate. A bottom electrode is disposed over one of the one or more lower interconnects. The bottom electrode includes a first material having a first electronegativity. A data storage layer separates the bottom electrode from a top electrode. The bottom electrode is between the data storage layer and the substrate. A reactivity reducing layer includes a second material and has a second electronegativity that is greater than or equal to the first electronegativity. The second material contacts a lower surface of the bottom electrode that faces the substrate.

公开(公告)号：US20210242400A1

公开(公告)日：2021-08-05

申请号：US17233755

申请日：2021-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yang Chen ,  Chun-Yang Tsai ,  Kuo-Ching Huang ,  Wen-Ting Chu ,  Pili Huang ,  Cheng-Jun Wu

IPC: H01L45/00 ,  H01L27/24

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes one or more lower interconnects arranged within a dielectric structure over a substrate. A bottom electrode is disposed over one of the one or more lower interconnects. The bottom electrode includes a first material having a first electronegativity. A data storage layer separates the bottom electrode from a top electrode. The bottom electrode is between the data storage layer and the substrate. A reactivity reducing layer includes a second material and has a second electronegativity that is greater than or equal to the first electronegativity. The second material contacts a lower surface of the bottom electrode that faces the substrate.

公开(公告)号：US20210098630A1

公开(公告)日：2021-04-01

申请号：US17117711

申请日：2020-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mickey Hsieh ,  Chun-Yang Tsai ,  Kuo-Ching Huang ,  Kuo-Chi Tu ,  Pili Huang ,  Cheng-Jun Wu ,  Chao-Yang Chen

IPC: H01L29/78 ,  H01L27/11507 ,  H01L49/02 ,  H01L29/66 ,  H01L29/51 ,  H01L27/1159 ,  H01L21/28

Abstract: Various embodiments of the present disclosure are directed towards a ferroelectric memory device. The ferroelectric memory device includes a pair of source/drain regions disposed in a semiconductor substrate. A gate dielectric is disposed over the semiconductor substrate and between the source/drain regions. A first conductive structure is disposed on the gate dielectric. A ferroelectric structure is disposed on the first conductive structure. A second conductive structure is disposed on the ferroelectric structure, where both the first conductive structure and the second conductive structure have an overall electronegativity that is greater than or equal to an overall electronegativity of the ferroelectric structure.

公开(公告)号：US11594632B2

公开(公告)日：2023-02-28

申请号：US17117711

申请日：2020-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mickey Hsieh ,  Chun-Yang Tsai ,  Kuo-Ching Huang ,  Kuo-Chi Tu ,  Pili Huang ,  Cheng-Jun Wu ,  Chao-Yang Chen

IPC: H01L29/78 ,  H01L27/11507 ,  H01L49/02 ,  H01L29/66 ,  H01L29/51 ,  H01L27/1159 ,  H01L21/28

Abstract: Various embodiments of the present disclosure are directed towards a ferroelectric memory device. The ferroelectric memory device includes a pair of source/drain regions disposed in a semiconductor substrate. A gate dielectric is disposed over the semiconductor substrate and between the source/drain regions. A first conductive structure is disposed on the gate dielectric. A ferroelectric structure is disposed on the first conductive structure. A second conductive structure is disposed on the ferroelectric structure, where both the first conductive structure and the second conductive structure have an overall electronegativity that is greater than or equal to an overall electronegativity of the ferroelectric structure.

公开(公告)号：US10985316B2

公开(公告)日：2021-04-20

申请号：US16359092

申请日：2019-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yang Chen ,  Chun-Yang Tsai ,  Kuo-Ching Huang ,  Wen-Ting Chu ,  Pili Huang ,  Cheng-Jun Wu

IPC: H01L27/088 ,  H01L21/8236 ,  H01L45/00 ,  H01L27/24

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes one or more lower interconnect layers arranged within a dielectric structure over a substrate. A bottom electrode is disposed over one of the one or more lower interconnect layers. A lower surface of the bottom electrode includes a material having a first electronegativity. A data storage layer separates the bottom electrode from a top electrode. A reactivity reducing layer contacts the lower surface of the bottom electrode. The reactivity reducing layer has a second electronegativity that is greater than or equal to the first electronegativity.