公开(公告)号：US20140369110A1

公开(公告)日：2014-12-18

申请号：US14290088

申请日：2014-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-hee CHO ,  Satoru YAMADA ,  Sang-ho SHIN ,  Sung-sam LEE

IPC: G11C11/406

CPC classification number: G11C11/40626 ,  G11C7/04 ,  G11C16/3418 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A semiconductor memory device includes: a memory unit including a first memory sub region including a first memory cell and a second memory sub region including a second memory cell; a temperature information obtaining unit that obtains temperature information; a temperature estimation unit that estimates a first temperature of the first memory sub region and a second temperature of the second memory sub region based on the temperature information; a first sub region control unit that controls the first memory sub region based on the first temperature; and a second sub region control unit that controls the second memory sub region based on the second temperature.

Abstract translation: 半导体存储器件包括：存储单元，包括包括第一存储单元的第一存储器子区域和包括第二存储器单元的第二存储器子区域; 获取温度信息的温度信息获取单元; 温度估计单元，其基于所述温度信息来估计所述第一存储器子区域的第一温度和所述第二存储器子区域的第二温度; 第一子区域控制单元，其基于第一温度来控制第一存储器子区域; 以及第二子区域控制单元，其基于第二温度来控制第二存储器子区域。

公开(公告)号：US20250113590A1

公开(公告)日：2025-04-03

申请号：US18976522

申请日：2024-12-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Huijung KIM ,  Satoru YAMADA ,  Sungwon YOO ,  Kyunghwan LEE ,  Jaeho HONG

IPC: H01L29/74 ,  H10B12/10

Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.

公开(公告)号：US20210225842A1

公开(公告)日：2021-07-22

申请号：US16999378

申请日：2020-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Satoru YAMADA ,  Sungwon YOO ,  Kyunghwan LEE ,  Jaeho HONG

IPC: H01L27/102 ,  H01L29/24

Abstract: A semiconductor memory device may include a first electrode and a second electrode, which are spaced apart from each other in a first direction, and a first semiconductor pattern, which is in contact with both of the first and second electrodes. The first semiconductor pattern may include first to fourth sub-semiconductor patterns, which are sequentially disposed in the first direction. The first and fourth sub-semiconductor patterns may be in contact with the first and second electrodes, respectively. The first and third sub-semiconductor patterns may be of a first conductivity type, and the second and fourth sub-semiconductor patterns may be of a second conductivity type different from the first conductivity type. Each of the first to fourth sub-semiconductor patterns may include a transition metal and a chalcogen element.

公开(公告)号：US20210036020A1

公开(公告)日：2021-02-04

申请号：US16942093

申请日：2020-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Han PARK ,  Yong Seok KIM ,  Hui-Jung KIM ,  Satoru YAMADA ,  Kyung Hwan LEE ,  Jae Ho HONG ,  Yoo Sang HWANG

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L49/02 ,  H01L29/06 ,  H01L29/45 ,  H01L29/786 ,  H01L29/78

Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.

公开(公告)号：US20170243973A1

公开(公告)日：2017-08-24

申请号：US15391888

申请日：2016-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungsam LEE ,  Junsoo KIM ,  Hyoshin AHN ,  Satoru YAMADA ,  Joohyun JEON ,  MoonYoung JEONG ,  Chunhyung CHUNG ,  Min Hee CHO ,  Kyo-Suk CHAE ,  Eunae CHOI

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L28/00 ,  H01L29/045 ,  H01L29/4236

Abstract: A semiconductor device including a semiconductor substrate including a trench, the semiconductor substrate having a crystal structure; and an insulating layer covering an inner sidewall of the trench, wherein the inner sidewall of the trench has at least one plane included in a {320} family of planes of the crystal structure or at least one plane similar to the {320} family of planes.

公开(公告)号：US20170005100A1

公开(公告)日：2017-01-05

申请号：US15139444

申请日：2016-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Hee CHO ,  Satoru YAMADA ,  Sung-Sam LEE ,  Jung-Bun LEE

IPC: H01L27/108

CPC classification number: H01L27/10897 ,  H01L23/522 ,  H01L23/5226

Abstract: A semiconductor device may include a plurality of dummy wirings formed on a substrate at different vertical levels and electrically floated and a plurality of dummy contact plugs each electrically connected between two adjacent dummy wirings of the plurality of dummy wiring of the plurality of dummy wirings. No dummy wiring of the plurality of dummy wirings is electrically connected to a terminal of any one of a plurality of transistors included in the substrate.

Abstract translation: 半导体器件可以包括形成在不同垂直级别的基板上的电浮置的多个虚拟布线和多个虚拟接触插塞，每个虚拟接触插头电连接在多个虚拟布线中的多个虚拟布线的两个相邻的虚拟布线之间。 多个虚拟布线的虚拟布线不与基板中包含的多个晶体管中的任一个晶体管的端子电连接。

公开(公告)号：US20160240619A1

公开(公告)日：2016-08-18

申请号：US15011820

申请日：2016-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin LEE ,  Junsoo KIM ,  Moonyoung JEONG ,  Satoru YAMADA ,  Dongsoo WOO ,  Jiyoung KIM

IPC: H01L29/40 ,  H01L29/423 ,  H01L27/088

CPC classification number: H01L29/402 ,  H01L27/088 ,  H01L27/10876 ,  H01L29/42392

Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

Abstract translation: 半导体器件可以包括被配置为在衬底中限定有源区的器件隔离区，设置在有源区中的有源栅极结构以及设置在器件隔离区中的场栅结构。 场栅结构可以包括栅极导电层。 有源栅极结构可以包括上有源栅极结构，其包括形成在上有源栅极结构下方并与上有源栅极结构垂直间隔开的栅极导电层和下有源栅极结构。 下部有源栅极结构可以包括栅极导电层。 场栅结构的栅极导电层的顶表面位于比上有源栅极结构的栅极导电层的底表面更低的水平处。

公开(公告)号：US20210319293A1

公开(公告)日：2021-10-14

申请号：US17224575

申请日：2021-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Hwan LEE ,  Yong Seok KIM ,  Hyun Cheol KIM ,  Satoru YAMADA ,  Sung Won YOO ,  Jae Ho HONG

IPC: G06N3/063 ,  G11C13/00 ,  G06N3/04 ,  G11C11/54

Abstract: A neuromorphic device includes a synaptic array, including input lines extending in a first direction and receiving input signals independently from axon circuits connected thereto, bit lines extending in a second direction crossing the first direction and outputting output signals, cell strings that each include at least two resistive memristor elements and a string select transistor in series between an input line and a bit line, electrode pads stacked and spaced apart from each other between the input and bit lines and connected to the string select transistor and at least two resistive memristor elements, a decoder to apply a string selection signal or a word line selection signal to the electrode pads, and neuron circuits, each connected to one of the bit lines connected to one of the cell strings, summing the output signals, converting and outputting the summed signal when it is more than a predetermined threshold.

公开(公告)号：US20190164985A1

公开(公告)日：2019-05-30

申请号：US16027887

申请日：2018-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok LEE ,  Junsoo KIM ,  Hui-Jung KIM ,  Bong-Soo KIM ,  Satoru YAMADA ,  Kyupil LEE ,  Sunghee HAN ,  HyeongSun HONG ,  Yoosang HWANG

IPC: H01L27/11556 ,  H01L23/532 ,  H01L27/11524 ,  H01L49/02 ,  G11C8/14 ,  G11C7/18

Abstract: A semiconductor memory device comprises a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also comprises a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer comprises semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

公开(公告)号：US20160322354A1

公开(公告)日：2016-11-03

申请号：US15209478

申请日：2016-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Suk CHAE ,  Satoru YAMADA ,  Sang-Yeon HAN ,  Young-Jin CHOI ,  Wook-Je KIM

IPC: H01L27/088 ,  H01L23/535 ,  H01L27/02 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L27/088 ,  H01L23/535 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/7833

Abstract: A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions. A common source region of the four transistors extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region. Four drain regions are provided, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region. Finally, four gate electrodes are provided, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions. A respective gate electrode includes a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction.

Abstract translation: 四晶体管布局可以包括限定有源区域的隔离区域，有源区域沿第一和第二不同方向延伸。 四个晶体管的共同源极区域从有源区域的中心沿着第一和第二方向延伸，以限定位于公共源极区域外的有源区域的四个象限。 设置四个漏极区，其中的一个位于四个象限中的相应一个中并与公共源极区间隔开。 最后，提供四个栅电极，其中的一个位于公共源极区域和四个漏极区域中的相应一个之间的四个象限中的相应一个中。 相应的栅电极包括顶点和第一和第二延伸部分，第一延伸部分从顶点沿着第一方向延伸，第二延伸部分沿着第二方向从顶点延伸。