公开(公告)号：US20220189968A1

公开(公告)日：2022-06-16

申请号：US17373539

申请日：2021-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin PARK ,  Kyujin KIM ,  Chulkwon PARK ,  Sunghee HAN

IPC: H01L27/108

Abstract: A semiconductor memory device includes a substrate comprising a memory cell region and a dummy cell region surrounding the memory cell region, the memory cell region including a plurality of memory cells, a plurality of active regions in the memory cell region, each of the plurality of active regions extending in a long axis direction, the long axis direction being a diagonal direction with respect to a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, each of the plurality of active regions having a first width in a short axis direction orthogonal to the long axis direction, and a plurality of dummy active regions in the dummy cell region, each extending in the long axis direction, each of the plurality of dummy active regions having a second width greater than the first width in the short axis direction.

公开(公告)号：US20190164985A1

公开(公告)日：2019-05-30

申请号：US16027887

申请日：2018-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok LEE ,  Junsoo KIM ,  Hui-Jung KIM ,  Bong-Soo KIM ,  Satoru YAMADA ,  Kyupil LEE ,  Sunghee HAN ,  HyeongSun HONG ,  Yoosang HWANG

IPC: H01L27/11556 ,  H01L23/532 ,  H01L27/11524 ,  H01L49/02 ,  G11C8/14 ,  G11C7/18

Abstract: A semiconductor memory device comprises a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also comprises a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer comprises semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

公开(公告)号：US20240138143A1

公开(公告)日：2024-04-25

申请号：US18545419

申请日：2023-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin PARK ,  Kyujin KIM ,  Chulkwon PARK ,  Sunghee HAN

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/09 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482

Abstract: A semiconductor memory device includes a substrate comprising a memory cell region and a dummy cell region surrounding the memory cell region, the memory cell region including a plurality of memory cells, a plurality of active regions in the memory cell region, each of the plurality of active regions extending in a long axis direction, the long axis direction being a diagonal direction with respect to a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, each of the plurality of active regions having a first width in a short axis direction orthogonal to the long axis direction, and a plurality of dummy active regions in the dummy cell region, each extending in the long axis direction, each of the plurality of dummy active regions having a second width greater than the first width in the short axis direction.

公开(公告)号：US20210202490A1

公开(公告)日：2021-07-01

申请号：US16943019

申请日：2020-07-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehwan CHO ,  Junghwan OH ,  Sangho LEE ,  Junwon LEE ,  Jinwoo BAE ,  Sunghee HAN ,  Yoosang HWANG

IPC: H01L27/108

Abstract: A semiconductor device may include a bottom sub-electrode on a substrate, a top sub-electrode on the bottom sub-electrode, a dielectric layer covering the bottom and top sub-electrodes, and a plate electrode on the dielectric layer. The top sub-electrode may include a step extending from a side surface thereof, which is adjacent to the bottom sub-electrode, to an inner portion of the top sub-electrode. The top sub-electrode may include a lower portion at a level that is lower than the step and an upper portion at a level which is higher than the step. A maximum width of the lower portion may be narrower than a minimum width of the upper portion. The maximum width of the lower portion may be narrower than a width of a top end of the bottom sub-electrode. The bottom sub-electrode may include a recess in a region adjacent to the top sub-electrode.

公开(公告)号：US20170200616A1

公开(公告)日：2017-07-13

申请号：US15377113

申请日：2016-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo-sun MIN ,  Yoonjae KIM ,  Sooho SHIN ,  Sunghee HAN

IPC: H01L21/306 ,  H01L21/822 ,  H01L21/265 ,  H01L21/768 ,  H01L21/283 ,  H01L21/308

CPC classification number: H01L21/30604 ,  H01L21/0337 ,  H01L21/26506 ,  H01L21/283 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/76895 ,  H01L21/8221 ,  H01L27/10823 ,  H01L27/10894

Abstract: A method of fabricating a semiconductor device includes sequentially forming a first insulation pattern and an etch stop pattern on a peripheral circuit area of a substrate, forming a first mask pattern on a cell array area of the substrate, the first mask pattern including a pair of first portions extending in parallel and a second portion covering a portion of a sidewall of the etch stop pattern and a portion of a sidewall of the first insulation pattern, forming a second insulation layer covering the etch stop pattern and the first mask pattern, partially etching the etch stop pattern and the second insulation layer to expose the second portion of the first mask pattern, and removing the second portion of the first mask pattern to divide the pair of first portions of the first mask pattern.

公开(公告)号：US20240114676A1

公开(公告)日：2024-04-04

申请号：US18525187

申请日：2023-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin PARK ,  Taehoon KIM ,  Kyujin KIM ,  Chulkwon PARK ,  Sunghee HAN ,  Yoosang HWANG

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315 ,  H10B12/482

Abstract: An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.

公开(公告)号：US20220246621A1

公开(公告)日：2022-08-04

申请号：US17725806

申请日：2022-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehwan CHO ,  Junghwan OH ,  Sangho LEE ,  Junwon LEE ,  Jinwoo BAE ,  Sunghee HAN ,  Yoosang HWANG

IPC: H01L27/108

Abstract: A semiconductor device may include a bottom sub-electrode on a substrate, a top sub-electrode on the bottom sub-electrode, a dielectric layer covering the bottom and top sub-electrodes, and a plate electrode on the dielectric layer. The top sub-electrode may include a step extending from a side surface thereof, which is adjacent to the bottom sub-electrode, to an inner portion of the top sub-electrode. The top sub-electrode may include a lower portion at a level that is lower than the step and an upper portion at a level which is higher than the step. A maximum width of the lower portion may be narrower than a minimum width of the upper portion. The maximum width of the lower portion may be narrower than a width of a top end of the bottom sub-electrode. The bottom sub-electrode may include a recess in a region adjacent to the top sub-electrode.

公开(公告)号：US20220344341A1

公开(公告)日：2022-10-27

申请号：US17558855

申请日：2021-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Huijung KIM ,  Myeongdong LEE ,  Inwoo KIM ,  Sunghee HAN

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/528

Abstract: A semiconductor device that includes a substrate including an active region and a contact recess. A gate electrode is disposed in the substrate and extends in a first direction. A bit line structure intersects the gate electrode and extends in a second direction intersecting the first direction. The bit line structure includes a direct contact disposed in the contact recess. A buried contact is disposed on the substrate and is electrically connected to the active region. A spacer structure is disposed between the bit line structure and the buried contact. The spacer structure includes a buried spacer disposed on a lateral side surface of the direct contact, and an air gap disposed on the buried spacer. The air gap exposes a lateral side surface of the bit line structure.

公开(公告)号：US20220181329A1

公开(公告)日：2022-06-09

申请号：US17328228

申请日：2021-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyoung CHOI ,  Woonghwi BAE ,  Jinwoo BAE ,  Chaelin YOON ,  Sunghee HAN ,  Sunwoo HEO ,  Deoksung HWANG

IPC: H01L27/108

Abstract: A semiconductor device includes first bit lines disposed on a substrate. Buried contacts disposed among first bit lines and connected to the substrate are provided. Landing pads are disposed on the buried contacts. Second bit lines are disposed on a peripheral area of the substrate. Upper surfaces of the second bit lines and the landing pads are coplanar with each other. First insulating patterns are disposed among the second bit lines. Second insulating patterns are disposed among the landing pads. Cell capacitors connected to the landing pads are disposed. The first insulating patterns include an insulating layer different from at least one insulating layer of the second insulating patterns.

公开(公告)号：US20210210492A1

公开(公告)日：2021-07-08

申请号：US16806667

申请日：2020-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Il HAN ,  Sunghee HAN ,  Yoosang HWANG

IPC: H01L27/108

Abstract: A semiconductor memory device is provided. The device includes a substrate including a cell region and a peripheral region; a plurality of lower electrodes disposed on the substrate in the cell region; a dielectric layer disposed on the plurality of lower electrodes; a metal containing layer disposed on the dielectric layer; a silicon germanium layer disposed on and electrically connected to the metal containing layer; a conductive pad disposed on and electrically connected to the silicon germanium layer; and an upper electrode contact plug disposed on and electrically connected to the conductive pad; The conductive pad extends from the upper electrode contact plug towards the peripheral region in a first direction, and the silicon germanium layer includes an edge portion that extends past the conductive pad in the first direction.