公开(公告)号：US20220246621A1

公开(公告)日：2022-08-04

申请号：US17725806

申请日：2022-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehwan CHO ,  Junghwan OH ,  Sangho LEE ,  Junwon LEE ,  Jinwoo BAE ,  Sunghee HAN ,  Yoosang HWANG

IPC: H01L27/108

Abstract: A semiconductor device may include a bottom sub-electrode on a substrate, a top sub-electrode on the bottom sub-electrode, a dielectric layer covering the bottom and top sub-electrodes, and a plate electrode on the dielectric layer. The top sub-electrode may include a step extending from a side surface thereof, which is adjacent to the bottom sub-electrode, to an inner portion of the top sub-electrode. The top sub-electrode may include a lower portion at a level that is lower than the step and an upper portion at a level which is higher than the step. A maximum width of the lower portion may be narrower than a minimum width of the upper portion. The maximum width of the lower portion may be narrower than a width of a top end of the bottom sub-electrode. The bottom sub-electrode may include a recess in a region adjacent to the top sub-electrode.

公开(公告)号：US20250133733A1

公开(公告)日：2025-04-24

申请号：US18886045

申请日：2024-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyesung PARK ,  Jonghyuk PARK ,  Seungji KANG ,  Seongeun KIM ,  Jinwoo BAE ,  Dongwon LEE ,  Juyeon HAN

IPC: H10B12/00

Abstract: A semiconductor device may include a substrate with a memory cell area including a first active area and a peripheral circuit area including a second active area, a capacitor structure including a first electrode connected to the first active area in the memory cell area, a second electrode including a silicon containing layer surrounding the first electrode on the memory cell area and a metal plate layer on the silicon containing layer, an interlayer insulating layer on the peripheral circuit area, and a capping insulating layer covering the capacitor structure on the memory cell area and covering the interlayer insulating layer on the peripheral circuit area. The capacitor structure may include a capacitor dielectric layer between the first and second electrode. The metal plate layer may be on an upper surface of the silicon containing layer and may not be on a side surface of the silicon containing layer.

公开(公告)号：US20220181329A1

公开(公告)日：2022-06-09

申请号：US17328228

申请日：2021-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyoung CHOI ,  Woonghwi BAE ,  Jinwoo BAE ,  Chaelin YOON ,  Sunghee HAN ,  Sunwoo HEO ,  Deoksung HWANG

IPC: H01L27/108

Abstract: A semiconductor device includes first bit lines disposed on a substrate. Buried contacts disposed among first bit lines and connected to the substrate are provided. Landing pads are disposed on the buried contacts. Second bit lines are disposed on a peripheral area of the substrate. Upper surfaces of the second bit lines and the landing pads are coplanar with each other. First insulating patterns are disposed among the second bit lines. Second insulating patterns are disposed among the landing pads. Cell capacitors connected to the landing pads are disposed. The first insulating patterns include an insulating layer different from at least one insulating layer of the second insulating patterns.

公开(公告)号：US20250048707A1

公开(公告)日：2025-02-06

申请号：US18604871

申请日：2024-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghoon KWON ,  Jinwoo BAE

IPC: H01L29/66 ,  H01L23/528 ,  H10B12/00

Abstract: A semiconductor device comprising: a substrate; a plurality of gate structures on the substrate, wherein the plurality of gate structures includes a first gate structure and a second gate structure that is adjacent the first gate structure; spacer structures on opposite sidewalls of the first gate structure; wherein the spacer structures comprise: insulating spacers on the opposite sidewalls of the first gate structure; an inner protective layer on the insulating spacers and an upper surface of the first gate structure; and an outer protective layer on at least a portion of the inner protective layer, an insulating filling layer on the spacer structures, wherein the insulating filling layer is between the first gate structure and the second gate structure; and an upper capping layer on an upper surface of the insulating filling layer, wherein the upper capping layer includes a same material as the insulating filling layer.

公开(公告)号：US20220278956A1

公开(公告)日：2022-09-01

申请号：US17638778

申请日：2020-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo BAE ,  Hyunjoo CHOI

IPC: H04L61/5007 ,  G06F13/362

Abstract: The disclosure relates to a 5th Generation (5G) or pre-5G communication system for supporting a higher data rate than a 4th Generation (4G) communication system such as Long Term Evolution (LTE). According to various embodiments of the disclosure, an apparatus of a base station in a wireless communication system is provided. The apparatus includes: a master Field Programmable Gate Array (FPGA); a plurality of slave FPGAs controlled by the master FPGA; and an address masker coupled to the master FPGA and the plurality of slave FPGAs, wherein the address masker is configured to: receive different address bits assigned respectively to the plurality of slave FPGAs by the master FPGA; for the different address bits, mask bit values at a specific position with the same value; and transmit masked address bits corresponding respectively to the plurality of slave FPGAs.

公开(公告)号：US20210202490A1

公开(公告)日：2021-07-01

申请号：US16943019

申请日：2020-07-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehwan CHO ,  Junghwan OH ,  Sangho LEE ,  Junwon LEE ,  Jinwoo BAE ,  Sunghee HAN ,  Yoosang HWANG

IPC: H01L27/108

Abstract: A semiconductor device may include a bottom sub-electrode on a substrate, a top sub-electrode on the bottom sub-electrode, a dielectric layer covering the bottom and top sub-electrodes, and a plate electrode on the dielectric layer. The top sub-electrode may include a step extending from a side surface thereof, which is adjacent to the bottom sub-electrode, to an inner portion of the top sub-electrode. The top sub-electrode may include a lower portion at a level that is lower than the step and an upper portion at a level which is higher than the step. A maximum width of the lower portion may be narrower than a minimum width of the upper portion. The maximum width of the lower portion may be narrower than a width of a top end of the bottom sub-electrode. The bottom sub-electrode may include a recess in a region adjacent to the top sub-electrode.

公开(公告)号：US20200312853A1

公开(公告)日：2020-10-01

申请号：US16829025

申请日：2020-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonyoung CHOI ,  Sungsoo YIM ,  Byeongmoo KANG ,  Seongmo KOO ,  Sejin PARK ,  Jinwoo BAE

IPC: H01L27/108 ,  H01L49/02

Abstract: A semiconductor device includes a transistor on a semiconductor substrate including a first area and a second area, and having a gate structure and an impurity area, a first interlayer insulating film covering the transistor, and having a contact plug electrically connected to the impurity area, a capacitor including a lower electrode on the first interlayer insulating film in the second area and electrically connected to the contact plug, a dielectric film coating a surface of the lower electrode, and an upper electrode on the dielectric film, and a support layer in contact with an upper side surface of the lower electrode to support the lower electrode, and extending to the first area, in which the support layer has a step between the first area and the second area.