公开(公告)号：US20240179893A1

公开(公告)日：2024-05-30

申请号：US18216745

申请日：2023-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangkyu SUN ,  Hyunyong KIM ,  Hyun-Jung KIM ,  Junhee PARK ,  Kyuwon WOO ,  Jiwon OH ,  Yoonyoung CHOI

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482

Abstract: A semiconductor device includes a substrate that includes an element separation film, an active region defined by the element separation film and arranged in a first direction, and a trench positioned across the active region and the element separation film, a bit line contact that is positioned within the trench and is connected to the active region, a bit line structure that is connected to the substrate through the bit line contact and that extends in a second direction different from the first direction across the active region, and a first contact spacer, a second contact spacer, and a third contact spacer within the trench and around the bit line contact, the first contact spacer being continuous within the trench, and each of the second contact spacer and the third contact spacer being separated into at least two discrete parts within the trench.

公开(公告)号：US20200312853A1

公开(公告)日：2020-10-01

申请号：US16829025

申请日：2020-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonyoung CHOI ,  Sungsoo YIM ,  Byeongmoo KANG ,  Seongmo KOO ,  Sejin PARK ,  Jinwoo BAE

IPC: H01L27/108 ,  H01L49/02

Abstract: A semiconductor device includes a transistor on a semiconductor substrate including a first area and a second area, and having a gate structure and an impurity area, a first interlayer insulating film covering the transistor, and having a contact plug electrically connected to the impurity area, a capacitor including a lower electrode on the first interlayer insulating film in the second area and electrically connected to the contact plug, a dielectric film coating a surface of the lower electrode, and an upper electrode on the dielectric film, and a support layer in contact with an upper side surface of the lower electrode to support the lower electrode, and extending to the first area, in which the support layer has a step between the first area and the second area.

公开(公告)号：US20210296431A1

公开(公告)日：2021-09-23

申请号：US17036731

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonyoung CHOI ,  SangJae PARK ,  Dongkyun LEE

IPC: H01L49/02

Abstract: An integrated circuit device including a lower electrode on a substrate, the lower electrode including a first lower electrode portion extending in a first direction perpendicular to a top surface of the substrate and including a first main region and a first top region, and a second lower electrode portion extending in the first direction on the first lower electrode portion and including a second main region and a second top region; a first top supporting pattern surrounding at least a portion of a side wall of the first top region of the first lower electrode portion; and a second top supporting pattern surrounding at least a portion of a side wall of the second top region of the second lower electrode portion, and the second lower electrode portion includes a protrusion protruding outward to the second top supporting pattern.

公开(公告)号：US20210050221A1

公开(公告)日：2021-02-18

申请号：US16863244

申请日：2020-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungjin KIM ,  Byung-Hyun LEE ,  Yoonyoung CHOI ,  Tae-Kyu KIM ,  Heesook CHEON ,  Bo-Wo CHOI ,  Hyun-Sil HONG

IPC: H01L21/311 ,  H01L21/48 ,  H01L21/027

Abstract: A method of fabricating a semiconductor device including preparing a substrate including a wafer inner region and a wafer edge region, the wafer inner region including a chip region and a scribe lane region, sequentially stacking a mold layer and a supporting layer on the substrate, forming a first mask layer on the supporting layer, the first mask layer including a first stepped region on the wafer edge region, forming a step-difference compensation pattern on the first stepped region, forming a second mask pattern including openings, on the first mask layer and the step-difference compensation pattern, and sequentially etching the first mask layer, the supporting layer, and the mold layer using the second mask pattern as an etch mask to form a plurality of holes in at least the mold layer may be provided.

公开(公告)号：US20220157822A1

公开(公告)日：2022-05-19

申请号：US17392775

申请日：2021-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung AHN ,  Yongseok AHN ,  Hyunyong KIM ,  Minsub UM ,  Ju Hyung WE ,  Joonkyu RHEE ,  Yoonyoung CHOI

IPC: H01L27/108

Abstract: A semiconductor memory device includes a substrate including a device isolation pattern defining an active pattern extending in a first direction and including first and second source/drain regions, a word line extending in a second direction intersecting the first direction, a bit line that is on the word line and electrically connected to the first source/drain region and that extends in a third direction that intersects the first and second directions, a bit-line spacer on a sidewall of the bit line, a storage node contact electrically connected to the second source/drain region and spaced apart from the bit line across the bit-line spacer, and a dielectric pattern between the bit-line spacer and the storage node contact. The bit-line spacer includes a first spacer covering the sidewall of the bit line and a second spacer between the dielectric pattern and the first spacer.

公开(公告)号：US20220149048A1

公开(公告)日：2022-05-12

申请号：US17357139

申请日：2021-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonkyu RHEE ,  Jiyoung AHN ,  Hyunyong KIM ,  Jamin KOO ,  Yongseok AHN ,  Minsub UM ,  Sangho LEE ,  Yoonyoung CHOI

IPC: H01L27/108

Abstract: A semiconductor device includes an active pattern on a substrate, a gate structure buried at an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure covering a lower sidewall of the bit line structure, a contact plug structure on the active pattern and adjacent to the bit line structure, and a capacitor on the contact plug structure. The lower spacer structure includes first and second lower spacers that are sequentially stacked from the lower sidewall of the bit line structure in a horizontal direction that is substantially parallel to an upper surface of the substrate, the first lower spacer includes an oxide, and contacts the lower sidewall of the bit line structure, but does not contact the contact plug structure, and the second lower spacer includes a material different from any of the materials of the first lower spacer.

公开(公告)号：US20210134942A1

公开(公告)日：2021-05-06

申请号：US16938286

申请日：2020-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungjin KIM ,  Sungsoo YIM ,  Suklae KIM ,  Hyukwoo KWON ,  Byunghyun LEE ,  Yoonyoung CHOI

IPC: H01L49/02 ,  H01L27/108

Abstract: An integrated circuit semiconductor device includes a plurality of cylindrical structures separated from each other on a substrate; and a plurality of supporters having an opening region exposing side surfaces of the plurality of cylindrical structures, the plurality of supporters being in contact with the side surfaces of the plurality of cylindrical structures and supporting the plurality of cylindrical structures, wherein each of the plurality of supporters has both side surfaces having slopes and has a top width that is less than a bottom width.