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    INTEGRATED CIRCUIT SEMICONDUCTOR DEVICE
    1.
    发明申请
    INTEGRATED CIRCUIT SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210134942A1

    公开(公告)日：2021-05-06

    申请号：US16938286

    申请日：2020-07-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seungjin KIM ,  Sungsoo YIM ,  Suklae KIM ,  Hyukwoo KWON ,  Byunghyun LEE ,  Yoonyoung CHOI

    IPC: H01L49/02 ,  H01L27/108

    Abstract: An integrated circuit semiconductor device includes a plurality of cylindrical structures separated from each other on a substrate; and a plurality of supporters having an opening region exposing side surfaces of the plurality of cylindrical structures, the plurality of supporters being in contact with the side surfaces of the plurality of cylindrical structures and supporting the plurality of cylindrical structures, wherein each of the plurality of supporters has both side surfaces having slopes and has a top width that is less than a bottom width.

    INTEGRATED CIRCUIT DEVICES
    2.
    发明申请
    INTEGRATED CIRCUIT DEVICES 有权

    公开(公告)号：US20220173002A1

    公开(公告)日：2022-06-02

    申请号：US17672939

    申请日：2022-02-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungheon LEE ,  Jaekang KOH ,  Hyukwoo KWON ,  Munjun KIM ,  Taejong HAN

    IPC: H01L23/29 ,  H01L23/31 ,  H01L21/02

    Abstract: A method of manufacturing an integrated circuit device, the method including forming a plurality of target patterns on a substrate such that an opening is defined between two adjacent target patterns; forming a pyrolysis material layer on the substrate such that the pyrolysis material layer partially fills the opening and exposes an upper surface and a portion of a sidewall of the two adjacent target patterns; and forming a material layer on the exposed upper surface and the exposed portion of the sidewall of the two adjacent target patterns, wherein, during the forming of the material layer, the material layer does not remain on a resulting surface of the pyrolysis material layer.

    INTEGRATED CIRCUIT DEVICES AND MANUFACTURING METHODS FOR THE SAME
    4.
    发明申请
    INTEGRATED CIRCUIT DEVICES AND MANUFACTURING METHODS FOR THE SAME 有权

    公开(公告)号：US20210125884A1

    公开(公告)日：2021-04-29

    申请号：US16919307

    申请日：2020-07-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungheon LEE ,  Jaekang KOH ,  Hyukwoo KWON ,  Munjun KIM ,  Taejong HAN

    IPC: H01L23/29 ,  H01L21/02 ,  H01L23/31

    Abstract: A method of manufacturing an integrated circuit device, the method including forming a plurality of target patterns on a substrate such that an opening is defined between two adjacent target patterns; forming a pyrolysis material layer on the substrate such that the pyrolysis material layer partially fills the opening and exposes an upper surface and a portion of a sidewall of the two adjacent target patterns; and forming a material layer on the exposed upper surface and the exposed portion of the sidewall of the two adjacent target patterns, wherein, during the forming of the material layer, the material layer does not remain on a resulting surface of the pyrolysis material layer.

    SEMICONDUCTOR DEVICES
    5.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20230135110A1

    公开(公告)日：2023-05-04

    申请号：US17940816

    申请日：2022-09-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hongrae KIM ,  Hyukwoo KWON

    IPC: H01L27/108

    Abstract: A semiconductor device includes a gate structure on a substrate, an insulating interlayer on the substrate and covering a sidewall of the gate structure, a capping layer on the gate structure and the insulating interlayer, a wiring on the capping layer, an insulation pattern on a bottom and a sidewall of an opening extending through the wiring and at least an upper portion of the capping layer, and an etch stop layer on the insulation pattern and the wiring. The insulation pattern includes a lower portion on the bottom of the opening and a lateral portion contacting the sidewall of the opening. A thickness of the lower portion of the insulation pattern from the bottom of the opening in a vertical direction is greater than a thickness of the lateral portion of the insulation pattern from the sidewall of the opening in a horizontal direction.

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200006345A1

    公开(公告)日：2020-01-02

    申请号：US16257260

    申请日：2019-01-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seongmin CHOO ,  Hyukwoo KWON ,  Jangseop KIM

    IPC: H01L27/108

    Abstract: A semiconductor memory device includes lower electrodes, each of the lower electrodes surrounding an inner space, an upper support layer on top surfaces of the lower electrodes, the upper support layer being on the inner spaces surrounded by the lower electrodes, and an upper electrode on the upper support layer, the upper electrode filling first and second regions, the second region penetrating the upper support layer, and the first region extending from the second region into between the lower electrodes. Each of the lower electrodes includes a first portion overlapping with the first region, a top surface of the first portion being exposed by the upper support layer, and a second portion covered by the upper support layer, a top surface of the second portion being in contact with the upper support layer.

    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
    7.
    发明公开
    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240196603A1

    公开(公告)日：2024-06-13

    申请号：US18508445

    申请日：2023-11-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kwanghee CHEON ,  Hyukwoo KWON ,  Munjun KIM ,  Sungyeon KIM ,  Younseok CHOI

    IPC: H10B12/00 ,  H01L29/423

    CPC classification number: H10B12/488 ,  H01L29/4236 ,  H10B12/50

    Abstract: An integrated circuit device includes a substrate having a plurality of active regions defined by a device isolation trench, a device isolation structure including an etching induction film and filling the device isolation trench, the etching induction film covering a bottom surface of the device isolation trench, a word line trench intersecting with the plurality of active regions and the device isolation structure and extending in a first lateral direction, a gate dielectric film covering an inner wall of the word line trench, and a word line filling a portion of the word line trench on the gate dielectric film, wherein each of the plurality of active regions includes a fin body portion under the word line and a saddle fin portion protruding from the fin body portion toward the word line, and the etching induction film is exposed by the word line trench.

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220085150A1

    公开(公告)日：2022-03-17

    申请号：US17536524

    申请日：2021-11-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyukwoo KWON ,  Ha-young YI ,  Byoungdeog CHOI ,  Seongmin CHOO

    IPC: H01L49/02 ,  H01L21/311 ,  H01L27/108

    Abstract: A semiconductor device includes a substrate, a bottom electrode on the substrate, a first support layer on the substrate next to a sidewall of the bottom electrode, a dielectric layer covering the sidewall and a top surface of the bottom electrode, and a top electrode on the dielectric layer. The bottom electrode includes a first part having a plurality of protrusions that protrude from a sidewall of the first part. The first part of the bottom electrode may be on the first support layer.

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