公开(公告)号：US20220165736A1

公开(公告)日：2022-05-26

申请号：US17368053

申请日：2021-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungsun RYU ,  Duckhee LEE ,  Junwon LEE ,  Younseok CHOI

IPC: H01L27/108

Abstract: A semiconductor device includes an active pattern on a substrate, a gate structure buried at an upper portion of the active pattern, a bit line structure on the active pattern, a spacer structure on a sidewall of the bit line structure, a contact plug structure contacting the spacer structure, an insulating interlayer structure partially penetrating through upper portions of the contact plug structure, the spacer structure and the bit line structure, and a capacitor on the contact plug structure. The spacer structure includes an air spacer including air. The insulating interlayer structure includes first and second insulating interlayers. The second insulating interlayer may include an insulation material different from that of the first insulating interlayer. A lower surface of the second insulating interlayer covers a top of the air spacer, and a lowermost surface of the first insulating interlayer is covered by the second insulating interlayer.

公开(公告)号：US20240196603A1

公开(公告)日：2024-06-13

申请号：US18508445

申请日：2023-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanghee CHEON ,  Hyukwoo KWON ,  Munjun KIM ,  Sungyeon KIM ,  Younseok CHOI

IPC: H10B12/00 ,  H01L29/423

CPC classification number: H10B12/488 ,  H01L29/4236 ,  H10B12/50

Abstract: An integrated circuit device includes a substrate having a plurality of active regions defined by a device isolation trench, a device isolation structure including an etching induction film and filling the device isolation trench, the etching induction film covering a bottom surface of the device isolation trench, a word line trench intersecting with the plurality of active regions and the device isolation structure and extending in a first lateral direction, a gate dielectric film covering an inner wall of the word line trench, and a word line filling a portion of the word line trench on the gate dielectric film, wherein each of the plurality of active regions includes a fin body portion under the word line and a saddle fin portion protruding from the fin body portion toward the word line, and the etching induction film is exposed by the word line trench.

公开(公告)号：US20240136393A1

公开(公告)日：2024-04-25

申请号：US18367090

申请日：2023-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyukwoo KWON ,  Munjun KIM ,  Junwon LEE ,  Younseok CHOI

IPC: H10B12/00

CPC classification number: H01L28/91 ,  H01L28/87 ,  H10B12/0335 ,  H10B12/315

Abstract: A capacitor structure includes a lower electrode structure having a lower electrode on a substrate and an electrode structure including electrode patterns stacked on the lower electrode in a vertical direction substantially perpendicular to an upper surface of the substrate, a dielectric pattern contacting the lower electrode structure, and an upper electrode contacting the dielectric pattern.

公开(公告)号：US20240234488A9

公开(公告)日：2024-07-11

申请号：US18367090

申请日：2023-09-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyukwoo KWON ,  Munjun KIM ,  Junwon LEE ,  Younseok CHOI

IPC: H10B12/00

CPC classification number: H01L28/91 ,  H01L28/87 ,  H10B12/0335 ,  H10B12/315

Abstract: A capacitor structure includes a lower electrode structure having a lower electrode on a substrate and an electrode structure including electrode patterns stacked on the lower electrode in a vertical direction substantially perpendicular to an upper surface of the substrate, a dielectric pattern contacting the lower electrode structure, and an upper electrode contacting the dielectric pattern.

公开(公告)号：US20240213017A1

公开(公告)日：2024-06-27

申请号：US18228220

申请日：2023-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younghun SUNG ,  Sunhye HWANG ,  Sangho RHA ,  Seungjae SIM ,  Younseok CHOI ,  Byungkeun HWANG ,  Youn Joung CHO

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/40 ,  C23C16/50 ,  C23C16/56 ,  H01L21/311

CPC classification number: H01L21/02164 ,  C23C16/345 ,  C23C16/401 ,  C23C16/50 ,  C23C16/56 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/31116 ,  H10B43/27

Abstract: A method of manufacturing an integrated circuit device, the method including forming a doped silicon oxide film on a substrate by supplying, onto the substrate, a silicon precursor, an oxidant, and at least two dopant sources including dopant elements that are different from each other such that the doped silicon oxide film includes at least two dopant elements; forming a vertical hole in the doped silicon oxide film by dry-etching the doped silicon oxide film; and forming a vertical structure in the vertical hole, wherein the silicon precursor includes a monosilane compound, a disilane compound, a siloxane compound, or a combination thereof, and the silicon precursor includes a Si—H functional group, and a C1-C10 oxy group or a C1-C10 organoamino group.

公开(公告)号：US20220223524A1

公开(公告)日：2022-07-14

申请号：US17481609

申请日：2021-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younseok CHOI ,  Byungsun PARK ,  Youngil LEE ,  Jaechul LEE ,  Jiwoon IM

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/768

Abstract: A semiconductor device includes a lower memory stack disposed on a substrate and including lower gate electrodes and a lower staircase structure, an upper memory stack including upper gate electrodes and an upper staircase structure, a lower interlayer insulating layer doped with an impurity and covering the lower staircase structure, the lower interlayer insulating layer having a doping concentration gradually increasing toward the lower staircase structure, an upper interlayer insulating layer doped with an impurity and covering the upper staircase structure and the lower interlayer insulating layer, the upper interlayer insulating layer having a doping concentration gradually increasing toward the upper staircase structure and the lower interlayer insulating layer, lower contact plugs and upper contact plugs contacting the lower gate electrodes and the upper gate electrodes, respectively.