公开(公告)号：US20230069868A1

公开(公告)日：2023-03-09

申请号：US17698476

申请日：2022-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongcheon KIM ,  Hyunchul LEE ,  Ki-Jeong KIM ,  Donghwi SHIN ,  Hyun-Sil HONG

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/027 ,  H01L23/522 ,  H01L23/528

Abstract: A method of fabricating a semiconductor device and a device fabricated thereby, the method including sequentially stacking an interlayer insulating layer, a porous dielectric layer, a first mask layer, and a second mask layer on a substrate; etching the second mask layer to form preliminary mask patterns; etching the preliminary mask patterns to form second mask patterns; etching the first mask layer using the second mask patterns as an etch mask to form first mask patterns; etching the porous dielectric layer using the first mask patterns as an etch mask to form grooves; and forming interconnection patterns in the grooves, respectively, wherein the porous dielectric layer includes SiOCH, and the first mask layer includes carbon-free silicon oxide (SiO2).

公开(公告)号：US20160104618A1

公开(公告)日：2016-04-14

申请号：US14715631

申请日：2015-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Sil HONG ,  Sungil CHO

IPC: H01L21/033 ,  H01L21/311 ,  H01L27/108 ,  H01L49/02 ,  H01L21/02 ,  H01L21/31 ,  H01L21/283

CPC classification number: H01L21/0332 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0334 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/10852 ,  H01L28/90

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a molding layer and a supporter layer on a semiconductor substrate, forming a multiple mask layer including a first mask layer and a second mask layer formed on the first mask layer, on the supporter layer. The first mask layer is formed of a material having an etch selectivity with respect to the molding layer and the second mask layer is formed of a material having an etch selectivity with respect to the supporter layer. The method includes forming a first mask pattern and a second mask pattern formed on the first mask pattern by patterning the multiple mask layer, etching the supporter layer by performing a first etching process using the second mask pattern as an etch mask, etching the molding layer, and forming a hole by performing a second etching process using the first mask pattern as an etch mask.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在半导体衬底上形成模制层和支撑层，在支撑层上形成包括形成在第一掩模层上的第一掩模层和第二掩模层的多掩模层。 第一掩模层由相对于模制层具有蚀刻选择性的材料形成，并且第二掩模层由相对于载体层具有蚀刻选择性的材料形成。 该方法包括通过对多个掩模层进行构图来形成形成在第一掩模图案上的第一掩模图案和第二掩模图案，通过使用第二掩模图案作为蚀刻掩模进行第一蚀刻工艺来蚀刻支撑层，蚀刻成型层 并且通过使用第一掩模图案作为蚀刻掩模执行第二蚀刻工艺来形成孔。

公开(公告)号：US20250157852A1

公开(公告)日：2025-05-15

申请号：US19024215

申请日：2025-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul LEE ,  Ki-Jeong KIM ,  Hwan LIM ,  Hyun-Sil HONG

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H10B12/00 ,  H10D64/27

Abstract: A semiconductor device includes a substrate having one or more inner surfaces defining trenches that define an active pattern of the substrate, the trenches including a first trench and a second trench which have different widths, a device isolation layer on the substrate such that the device isolation layer at least partially fills the trenches, and a word line intersecting the active pattern. The device isolation layer includes a first isolation pattern covering a portion of the second trench, a second isolation pattern on the first isolation pattern and covering a remaining portion of the second trench, and a filling pattern filling the first trench under the word line. A top surface of the second isolation pattern is located at a higher level than a top surface of the filling pattern.

公开(公告)号：US20230013061A1

公开(公告)日：2023-01-19

申请号：US17668452

申请日：2022-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul LEE ,  Ki-Jeong KIM ,  Hwan LIM ,  Hyun-Sil HONG

IPC: H01L21/762 ,  H01L29/423 ,  H01L21/02 ,  H01L27/108

Abstract: A semiconductor device includes a substrate having one or more inner surfaces defining trenches that define an active pattern of the substrate, the trenches including a first trench and a second trench which have different widths, a device isolation layer on the substrate such that the device isolation layer at least partially fills the trenches, and a word line intersecting the active pattern. The device isolation layer includes a first isolation pattern covering a portion of the second trench, a second isolation pattern on the first isolation pattern and covering a remaining portion of the second trench, and a filling pattern filling the first trench under the word line. A top surface of the second isolation pattern is located at a higher level than a top surface of the filling pattern.

公开(公告)号：US20210050221A1

公开(公告)日：2021-02-18

申请号：US16863244

申请日：2020-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungjin KIM ,  Byung-Hyun LEE ,  Yoonyoung CHOI ,  Tae-Kyu KIM ,  Heesook CHEON ,  Bo-Wo CHOI ,  Hyun-Sil HONG

IPC: H01L21/311 ,  H01L21/48 ,  H01L21/027

Abstract: A method of fabricating a semiconductor device including preparing a substrate including a wafer inner region and a wafer edge region, the wafer inner region including a chip region and a scribe lane region, sequentially stacking a mold layer and a supporting layer on the substrate, forming a first mask layer on the supporting layer, the first mask layer including a first stepped region on the wafer edge region, forming a step-difference compensation pattern on the first stepped region, forming a second mask pattern including openings, on the first mask layer and the step-difference compensation pattern, and sequentially etching the first mask layer, the supporting layer, and the mold layer using the second mask pattern as an etch mask to form a plurality of holes in at least the mold layer may be provided.