公开(公告)号：US20240047247A1

公开(公告)日：2024-02-08

申请号：US18184418

申请日：2023-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chansoo KANG ,  Daewon KANG ,  Sangki NAM ,  Jungmo YANG ,  Changsoon LIM ,  Sungho JANG ,  Jonghun PI ,  Youngil KANG ,  Yoonjae KIM ,  Ilwoo KIM ,  Jongmu KIM ,  Yongbeom PARK

IPC: H01L21/67 ,  H01J37/32

CPC classification number: H01L21/67253 ,  H01J37/32944 ,  H01J2237/221

Abstract: A semiconductor process device includes a chamber housing defining an internal region and a plurality of electrostatic chucks within the internal region. The chamber housing includes a window, and a light collection unit including a first optical system and a second optical system located at different positions on the window. A plurality of first optical pickup units are connected to the first optical system, and a plurality of second optical pickup units are connected to the second optical system. A sensor includes a plurality of photodetectors that are configured to convert a first optical signal transmitted by the plurality of first optical pickup units and a second optical signal transmitted by the plurality of second optical pickup units into electrical signals. A processor is configured to generate a spatial image of the internal region of the chamber housing using the electrical signals output by the plurality of photodetectors, and determine a location at which an arc occurs in the internal region of the chamber housing based on the spatial image.

公开(公告)号：US20240105790A1

公开(公告)日：2024-03-28

申请号：US18337952

申请日：2023-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsoo PARK ,  Bongjin KUH ,  Bongsoo KIM ,  Yoonjae KIM ,  Dongsoo WOO

IPC: H01L29/423 ,  H10B12/00

CPC classification number: H01L29/4236 ,  H01L28/60 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

Abstract: Provided is an integrated circuit device including a substrate including a first active area and a second active area each extending in a first direction, a bit line extending in the first direction in a first trench of the substrate and arranged between the first active area and the second active area in a second direction perpendicular to the first direction, a contact structure including a lower contact contacting the bit line and an upper contact contacting the first active area, a word line extending in the second direction in a second trench of the substrate, a plurality of landing pads on the substrate, and a capacitor structure including a plurality of lower electrodes on the plurality of landing pads, wherein the bit line and the word line are buried under an upper surface of the substrate.

公开(公告)号：US20170200616A1

公开(公告)日：2017-07-13

申请号：US15377113

申请日：2016-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo-sun MIN ,  Yoonjae KIM ,  Sooho SHIN ,  Sunghee HAN

IPC: H01L21/306 ,  H01L21/822 ,  H01L21/265 ,  H01L21/768 ,  H01L21/283 ,  H01L21/308

CPC classification number: H01L21/30604 ,  H01L21/0337 ,  H01L21/26506 ,  H01L21/283 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/76895 ,  H01L21/8221 ,  H01L27/10823 ,  H01L27/10894

Abstract: A method of fabricating a semiconductor device includes sequentially forming a first insulation pattern and an etch stop pattern on a peripheral circuit area of a substrate, forming a first mask pattern on a cell array area of the substrate, the first mask pattern including a pair of first portions extending in parallel and a second portion covering a portion of a sidewall of the etch stop pattern and a portion of a sidewall of the first insulation pattern, forming a second insulation layer covering the etch stop pattern and the first mask pattern, partially etching the etch stop pattern and the second insulation layer to expose the second portion of the first mask pattern, and removing the second portion of the first mask pattern to divide the pair of first portions of the first mask pattern.