公开(公告)号：US20250107022A1

公开(公告)日：2025-03-27

申请号：US18907611

申请日：2024-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jooyoung KANG ,  Bongsoo KIM ,  Sejin PARK ,  Wanju BYUN ,  Sujeong CHO ,  Hyunju HONG

IPC: H05K5/02

Abstract: An electronic device includes a first housing, a second housing slidably coupled to the first housing, and a drive part. The drive part provides a driving force for sliding the second housing and includes a pinion gear and a drive motor configured to rotate the pinion gear. The electronic device further includes a rack gear and a guide structure. The rack gear is gear-coupled to the pinion gear to reciprocate in a predetermined section in accordance with a rotation of the pinion gear. The guide structure includes an accommodation space configured to accommodate at least a part of the rack gear and to guide the moving rack gear.

公开(公告)号：US20240032280A1

公开(公告)日：2024-01-25

申请号：US18224802

申请日：2023-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejin PARK ,  Kyujin KIM ,  Bongsoo KIM ,  Huijung KIM ,  Chulkwon PARK ,  Gyunghyun YOON ,  Heejae CHAE

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053

Abstract: An Integrated Circuit (IC) semiconductor device includes: field insulating layers buried in field trenches disposed apart from each other inside a substrate; active regions defined by the field insulating layers; and active fins disposed on the active regions and protruding from surfaces of the field insulating layers. The field insulating layers include a first subfield insulating layer and a second subfield insulating layer, and a surface of the first subfield insulating layer is disposed at a level lower than a level of a surface of the second subfield insulating layer.

公开(公告)号：US20250140619A1

公开(公告)日：2025-05-01

申请号：US18927331

申请日：2024-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongsoo KIM ,  Chobi KIM ,  Pyunghwa HAN

IPC: H01L23/14 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes: a first interconnection structure; an expanded layer arranged on the first interconnection structure, the expanded layer comprising a plurality of expanded base layers; a semiconductor chip arranged in a mounting space and electrically connected to the first interconnection structure; a filling insulating layer configured to fill the mounting space; and a second interconnection structure arranged on the expanded layer and the filling insulating layer, the second interconnection structure electrically connected to the first interconnection structure through a plurality of via structures, in which a surface of a lowermost expanded base layer among the plurality of expanded base layers is positioned at a higher vertical level than a surface of the filling insulating layer, and a sink space is confined by the expanded layer and the filling insulating layer under a surface of the lowermost expanded base layer among the plurality of expanded base layers.

公开(公告)号：US20240290868A1

公开(公告)日：2024-08-29

申请号：US18404607

申请日：2024-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin PARK ,  Bongsoo KIM ,  Huijung KIM

IPC: H01L29/66 ,  H01L29/06 ,  H10B12/00

CPC classification number: H01L29/6656 ,  H01L29/0649 ,  H10B12/315

Abstract: A semiconductor device includes a first structure including a first impurity region, a second impurity region, and an isolation region, a second structure on the first structure and including a contact opening penetrating through the second structure and exposing the first impurity region, a pattern structure including a contact portion connected to the first impurity region in the contact opening, and a line portion on the contact portion and the second structure, and a spacer structure between a side surface of the contact opening and the contact portion. The spacer structure includes a first spacer layer on the side surface of the contact opening, and a second spacer layer between the first spacer layer and the contact portion. A lower end of the second spacer layer is at a higher level than a lower surface of the contact portion.

公开(公告)号：US20240105790A1

公开(公告)日：2024-03-28

申请号：US18337952

申请日：2023-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsoo PARK ,  Bongjin KUH ,  Bongsoo KIM ,  Yoonjae KIM ,  Dongsoo WOO

IPC: H01L29/423 ,  H10B12/00

CPC classification number: H01L29/4236 ,  H01L28/60 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

Abstract: Provided is an integrated circuit device including a substrate including a first active area and a second active area each extending in a first direction, a bit line extending in the first direction in a first trench of the substrate and arranged between the first active area and the second active area in a second direction perpendicular to the first direction, a contact structure including a lower contact contacting the bit line and an upper contact contacting the first active area, a word line extending in the second direction in a second trench of the substrate, a plurality of landing pads on the substrate, and a capacitor structure including a plurality of lower electrodes on the plurality of landing pads, wherein the bit line and the word line are buried under an upper surface of the substrate.

公开(公告)号：US20240365535A1

公开(公告)日：2024-10-31

申请号：US18397014

申请日：2023-12-27

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Jongmin KIM ,  Kiseok LEE ,  Bongsoo KIM ,  Chan-Sic YOON

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/315 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor device includes a first active pattern including a first edge portion and a second edge portion, which are spaced apart from each other in a first direction; a first word line between the first edge portion of the first active pattern and the second edge portion of the first active pattern and extending in a second direction that crosses the first direction; a bit line on the first edge portion of the first active pattern and extending in a third direction that crosses the first direction and the second direction; and a storage node contact on the second edge portion of the first active pattern, wherein a top surface of the first edge portion is at a level higher than a top surface of the second edge portion.

公开(公告)号：US20240130112A1

公开(公告)日：2024-04-18

申请号：US18464475

申请日：2023-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin PARK ,  Bongsoo KIM ,  Huijung KIM

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/485 ,  H10B12/488

Abstract: Provided is an integrated circuit device including a substrate that has an active region defined by a plurality of device separation regions, a word line on the substrate and arranged in a word line trench that extends in a first horizontal direction, a bit line on the word line and extending in a second horizontal direction orthogonal to the first horizontal direction, a pad on the active region and having a horizontal width that is larger than the active region, and a bit line contact electrically connecting the bit line to the active region, wherein a level of a lowermost surface of the additional pad is at a same vertical level as a level of a lowermost surface of the bit line contact.

公开(公告)号：US20230199953A1

公开(公告)日：2023-06-22

申请号：US18107129

申请日：2023-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongsoo KIM ,  Gyeongmin JIN ,  Hakjoon KIM ,  Jaebum LEE

IPC: H05K1/11 ,  H05K3/34

CPC classification number: H05K1/111 ,  H05K3/3436 ,  H05K2201/099

Abstract: An electronic device according to an embodiment may include: a Printed Circuit Board (PCB) including a first face and a second face; a semiconductor chip mounted on the second face; a conductive pad disposed on the second face; a solder resist layer disposed on the second face and including an aperture; an arc-shaped opening having an inner diameter and an outer diameter, disposed along an outer periphery of the conductive pad and in the aperture; and at least one external terminal disposed on the semiconductor chip and bonded to the conductive pad. The conductive pad may include: a first region having a smaller diameter than the outer diameter; and at least one second region extending from the first region in a first outer circumferential direction, and located at least in part between both ends of the opening. In addition, various embodiments recognized through the specification may also be possible.