公开(公告)号：US20180158918A1

公开(公告)日：2018-06-07

申请号：US15868620

申请日：2018-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin LEE ,  Junsoo KIM ,  Moonyoung JEONG ,  Satoru YAMADA ,  Dongsoo WOO ,  Jiyoung KIM

IPC: H01L29/40 ,  H01L27/108 ,  H01L29/423

CPC classification number: H01L29/402 ,  B82Y10/00 ,  H01L21/84 ,  H01L27/088 ,  H01L27/10876 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78639 ,  H01L29/78696

Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

公开(公告)号：US20180158826A1

公开(公告)日：2018-06-07

申请号：US15661121

申请日：2017-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Hee CHO ,  Satoru YAMADA ,  Junsoo KIM ,  Honglae PARK ,  Wonsok LEE ,  Namho JEON

IPC: H01L27/108 ,  H01L29/20 ,  H01L29/161

CPC classification number: H01L27/10805 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/161 ,  H01L29/20

Abstract: A semiconductor memory device includes a substrate having an active region, word lines extending across the active region, a bit line on the active region between the word lines, a bit line node contact between the bit line and the active region, and a storage node contact on an end portion of the active region, wherein one or more of the bit line node contact or the storage node contact include silicon germanium.

公开(公告)号：US20210358913A1

公开(公告)日：2021-11-18

申请号：US17092593

申请日：2020-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Huijung KIM ,  Satoru YAMADA ,  Sungwon YOO ,  Kyunghwan LEE ,  Jaeho HONG

IPC: H01L27/102 ,  H01L29/74

Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.

公开(公告)号：US20210074914A1

公开(公告)日：2021-03-11

申请号：US16592041

申请日：2019-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Hwan LEE ,  Yong Seok KIM ,  Tae Hun KIM ,  Seok Han PARK ,  Satoru YAMADA ,  Jae Ho HONG

IPC: H01L45/00 ,  H01L27/24

Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including alternating gate electrodes and insulating layers stacked along a first direction, a vertical opening through the stack structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening, and a variable resistive material on the semiconductor layer, a vacancy concentration in the variable resistive material varies along its width to have a higher concentration closer to a center of the channel structure than to the semiconductor layer, and an impurity region on the substrate, the semiconductor layer contacting the impurity region at a bottom of the channel structure.

公开(公告)号：US20160260813A1

公开(公告)日：2016-09-08

申请号：US14854272

申请日：2015-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunae CHO ,  Dongjin LEE ,  Ji Eun LEE ,  Kyoung-Ho JUNG ,  Dong Su KO ,  Yongsu KIM ,  Jiho YOO ,  Sung HEO ,  Hyun PARK ,  Satoru YAMADA ,  Moonyoung JEONG ,  Sungjin KIM ,  Gyeongsu PARK ,  Han Jin LIM

IPC: H01L29/423 ,  H01L29/51 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/4236 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate including a trench. The semiconductor device further includes a gate electrode disposed in the trench, and a gate insulating film disposed between the substrate and the gate electrode. The gate electrode includes a gate conductor and a metal element, and an effective work function of the gate electrode is less than an effective work function of the gate conductor.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括包括沟槽的衬底。 半导体器件还包括设置在沟槽中的栅极电极和设置在衬底和栅电极之间的栅极绝缘膜。 栅电极包括栅极导体和金属元件，并且栅电极的有效功函数小于栅极导体的有效功函数。

公开(公告)号：US20230352548A1

公开(公告)日：2023-11-02

申请号：US18219525

申请日：2023-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunae CHO ,  Dongjin LEE ,  Ji Eun LEE ,  Kyoung-Ho JUNG ,  Dong Su KO ,  Yongsu KIM ,  Jiho YOO ,  Sung HEO ,  Hyun PARK ,  Satoru YAMADA ,  Moonyoung JEONG ,  Sungjin KIM ,  Gyeongsu PARK ,  Han Jin LIM

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/4236 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate including a trench. The semiconductor device further includes a gate electrode disposed in the trench, and a gate insulating film disposed between the substrate and the gate electrode. The gate electrode includes a gate conductor and a metal element, and an effective work function of the gate electrode is less than an effective work function of the gate conductor.

公开(公告)号：US20230019055A1

公开(公告)日：2023-01-19

申请号：US17954844

申请日：2022-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Han PARK ,  Yong Seok KIM ,  Hui-Jung KIM ,  Satoru YAMADA ,  Kyung Hwan LEE ,  Jae Ho HONG ,  Yoo Sang HWANG

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L49/02 ,  H01L29/78 ,  H01L29/45 ,  H01L29/786 ,  H01L29/06

Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.

公开(公告)号：US20210335798A1

公开(公告)日：2021-10-28

申请号：US17227793

申请日：2021-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Hwan LEE ,  Yong Seok KIM ,  Hyun Cheol KIM ,  Satoru YAMADA ,  Sung Won YOO ,  Jae Ho HONG

IPC: H01L27/1156 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11551

Abstract: Provided is a semiconductor memory device. The semiconductor memory device comprises a first semiconductor pattern including a first impurity region, a second impurity region, and a channel region, the first impurity region spaced apart from a substrate in a first direction and having a first conductivity type, the second impurity region having a second conductivity type different from the first conductivity type, and the channel region between the first impurity region and the second impurity region, a first conductive connection line connected to the first impurity region and extending in a second direction different from the first direction and a first gate structure extending in the first direction and including a first gate electrode and a first gate insulating film, wherein the first gate electrode penetrates the channel region and the first gate insulating film is between the first gate electrode and the semiconductor pattern.

公开(公告)号：US20200303504A1

公开(公告)日：2020-09-24

申请号：US16546506

申请日：2019-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hae-in JUNG ,  Moon-young JEONG ,  Joon HAN ,  Satoru YAMADA

IPC: H01L29/10 ,  H01L27/02 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L27/088 ,  H01L27/108 ,  H01L21/8234 ,  H01L21/306 ,  H01L27/11526 ,  H01L27/11573

Abstract: Provided are a multi-direction channel transistor having a gate having an increased effective width and a multi-direction channel, and a semiconductor device including the multi-direction channel transistor, wherein the multi-direction channel transistor includes at least one fin on an active region on a substrate and disposed adjacent to a recess extending in a first direction; a gate line extending in a second direction crossing the first direction and covering at least a portion of the at least one fin and the recess; source/drain regions on the active region at both sides of the gate line; and a channel region in the active region under the gate line between the source/drain regions, wherein the first direction is diagonal to the second direction, and a dielectric film under the gate line has substantially the same thickness on both the at least one fin and the recess.

公开(公告)号：US20190198626A1

公开(公告)日：2019-06-27

申请号：US16288910

申请日：2019-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin LEE ,  Junsoo KIM ,  Moonyoung JEONG ,  Satoru YAMADA ,  Dongsoo WOO ,  Jiyoung KIM

IPC: H01L29/40 ,  H01L27/108 ,  H01L29/66 ,  B82Y10/00 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L21/84

CPC classification number: H01L29/402 ,  B82Y10/00 ,  H01L21/84 ,  H01L27/088 ,  H01L27/10876 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78639 ,  H01L29/78696

Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.