公开(公告)号：US20160322354A1

公开(公告)日：2016-11-03

申请号：US15209478

申请日：2016-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Suk CHAE ,  Satoru YAMADA ,  Sang-Yeon HAN ,  Young-Jin CHOI ,  Wook-Je KIM

IPC: H01L27/088 ,  H01L23/535 ,  H01L27/02 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L27/088 ,  H01L23/535 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/7833

Abstract: A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions. A common source region of the four transistors extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region. Four drain regions are provided, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region. Finally, four gate electrodes are provided, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions. A respective gate electrode includes a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction.

Abstract translation: 四晶体管布局可以包括限定有源区域的隔离区域，有源区域沿第一和第二不同方向延伸。 四个晶体管的共同源极区域从有源区域的中心沿着第一和第二方向延伸，以限定位于公共源极区域外的有源区域的四个象限。 设置四个漏极区，其中的一个位于四个象限中的相应一个中并与公共源极区间隔开。 最后，提供四个栅电极，其中的一个位于公共源极区域和四个漏极区域中的相应一个之间的四个象限中的相应一个中。 相应的栅电极包括顶点和第一和第二延伸部分，第一延伸部分从顶点沿着第一方向延伸，第二延伸部分沿着第二方向从顶点延伸。

公开(公告)号：US20160300932A1

公开(公告)日：2016-10-13

申请号：US15187430

申请日：2016-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-In Choi ,  Gyeom KIM ,  Hong-Sik YOON ,  Bon-Young KOO ,  Wook-Je KIM

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/66545 ,  H01L29/785 ,  H01L2924/13067

Abstract: A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern, a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration, and a liner on the multi-channel active pattern, the liner extending on lateral surfaces of the first region and not extending on a top surface of the first region. Related fabrication methods are also described.

Abstract translation: 半导体器件包括衬底上的栅极图案，栅极图案下方的跨越栅极图案的多通道有源图案，并且具有不与栅极图案重叠的第一区域和与栅极图案重叠的第二区域， 多通道活性图案沿着第一区域的外周边并且包括具有浓度的杂质和多通道活性图案上的衬垫，衬垫在第一区域的侧表面上延伸并且不在第一区域的顶表面上延伸 第一个地区。 还描述了相关的制造方法。