公开(公告)号：US20150145056A1

公开(公告)日：2015-05-28

申请号：US14565903

申请日：2014-12-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Chan Lee ,  Seung-Jae Lee ,  Sang-Bom Kang ,  Dae-Young Kwak ,  Myeong-Cheol Kim ,  Yong-Ho Jeon

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L21/764 ,  H01L27/0886 ,  H01L27/1116 ,  H01L27/1211

Abstract: A semiconductor device including: a first gate pattern disposed in a peripheral region of a substrate; a second gate pattern disposed in a cell region of the substrate; a first insulator formed on sidewalls of the first gate pattern; and a second insulator formed on sidewalls of the second gate pattern, wherein a dielectric constant of the first insulator is different from a dielectric constant of the second insulator, and wherein a height of the second insulator is greater than a height of the second gate pattern.

Abstract translation: 一种半导体器件，包括：设置在衬底的周边区域中的第一栅极图案; 设置在所述基板的单元区域中的第二栅极图案; 形成在第一栅极图案的侧壁上的第一绝缘体; 以及形成在所述第二栅极图案的侧壁上的第二绝缘体，其中所述第一绝缘体的介电常数不同于所述第二绝缘体的介电常数，并且其中所述第二绝缘体的高度大于所述第二栅极图案的高度 。

公开(公告)号：US20150076617A1

公开(公告)日：2015-03-19

申请号：US14548871

申请日：2014-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Cheol Kim ,  Il-Sup Kim ,  Cheol Kim ,  Jong-Chan Shin ,  Jong-Wook Lee ,  Choong-Ho Lee ,  Si-Young Choi ,  Jong-Seo Hong

IPC: H01L27/088 ,  H01L29/16

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/16

Abstract: Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.

Abstract translation: 提供了形成半导体器件的图案的方法。 所述方法可以包括在半导体衬底上形成硬掩模膜。 所述方法可以包括形成在硬掩模膜上彼此间隔开的第一和第二牺牲膜图案。 所述方法可以包括在第一牺牲膜图案的相对侧壁上形成第一间隔物，以及在第二牺牲膜图案的相对侧壁上形成第二间隔物。 所述方法可以包括去除第一和第二牺牲膜图案。 所述方法可以包括修整第二间隔物，使得第二间隔物的线宽变得小于第一间隔物的线宽。 所述方法可以包括通过使用第一间隔物和修剪的第二间隔物作为蚀刻掩模蚀刻硬掩模膜来形成第一和第二硬掩模膜图案。

公开(公告)号：US11830775B2

公开(公告)日：2023-11-28

申请号：US17698487

申请日：2022-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul Sun ,  Myeong-Cheol Kim ,  Kyoung-Sub Shin

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/306 ,  H01L21/308 ,  H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L23/535 ,  G06F7/505 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  G06F30/39 ,  G06F30/398 ,  G06F119/12 ,  G06F117/12

CPC classification number: H01L21/823807 ,  G06F7/505 ,  G06F30/39 ,  G06F30/398 ,  H01L21/308 ,  H01L21/30608 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  G06F2117/12 ,  G06F2119/12

Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.

公开(公告)号：US09484458B2

公开(公告)日：2016-11-01

申请号：US14602716

申请日：2015-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Wook Lee ,  Myeong-Cheol Kim ,  Sang-Min Lee ,  Young-Ju Park ,  Hyung-Yong Kim ,  Myung-Hoon Jung

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/11

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/11 ,  H01L29/66636 ,  H01L29/78

Abstract: A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from each other at a second pitch different from the first pitch, implanting an etch rate adjusting dopant into the second region to form implanted regions, while blocking the first region, forming a first trench by etching the first region between the plurality of first gates, and forming a second trench by etching the second region between the plurality of second gates.

Abstract translation: 半导体器件的制造方法包括提供具有第一区域和第二区域的衬底，在衬底的第一区域中形成多个第一栅极，使得第一栅极以第一间距相互间隔开， 在所述衬底的所述第二区域中形成多个第二栅极，使得所述第二栅极以不同于所述第一间距的第二间距彼此间隔开，将蚀刻速率调节掺杂剂注入所述第二区域以形成注入区域， 同时阻挡第一区域，通过蚀刻多个第一栅极之间的第一区域形成第一沟槽，并且通过蚀刻多个第二栅极之间的第二区域形成第二沟槽。

公开(公告)号：US09287161B2

公开(公告)日：2016-03-15

申请号：US14497501

申请日：2014-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hyun Lee ,  Myeong-Cheol Kim ,  Yoo-Jung Lee ,  Il-Sup Kim ,  Seung-Ju Park

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895

Abstract: A method of manufacturing a wiring includes sequentially forming a first insulation layer, a first layer, and a second layer on a substrate, etching an upper portion of the second layer a plurality of times to form a second layer pattern including a first recess having a shape of a staircase, etching a portion of the second layer pattern and a portion of the first layer under the first recess to form a first layer pattern including a second recess having a shape of a staircase similar to the first recess, etching a portion of the first layer pattern under the second recess to form a first opening exposing a portion of a top surface of the first insulation layer, etching the exposed portion of the first insulation layer to form a second opening through the first insulation layer, and forming a wiring filling the second opening.

Abstract translation: 一种制造布线的方法包括：在基板上依次形成第一绝缘层，第一层和第二层，多次蚀刻第二层的上部以形成第二层图案，该第二层图案包括具有第 形成阶梯，蚀刻第二层图案的一部分和在第一凹部下方的第一层的一部分，以形成第一层图案，该第一层图案包括具有类似于第一凹部的阶梯形状的第二凹部，蚀刻部分 在第二凹部下方的第一层图案，以形成暴露第一绝缘层的顶表面的一部分的第一开口，蚀刻第一绝缘层的暴露部分以形成穿过第一绝缘层的第二开口，以及形成布线 填补第二个开口。

公开(公告)号：US08906757B2

公开(公告)日：2014-12-09

申请号：US13674386

申请日：2012-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Cheol Kim ,  Il-Sup Kim ,  Cheol Kim ,  Jong-Chan Shin ,  Jong-Wook Lee ,  Choong-Ho Lee ,  Si-Young Choi ,  Jong-Seo Hong

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/308 ,  H01L21/033

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/16

Abstract: Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.

Abstract translation: 提供了形成半导体器件的图案的方法。 所述方法可以包括在半导体衬底上形成硬掩模膜。 所述方法可以包括形成在硬掩模膜上彼此间隔开的第一和第二牺牲膜图案。 所述方法可以包括在第一牺牲膜图案的相对侧壁上形成第一间隔物，以及在第二牺牲膜图案的相对侧壁上形成第二间隔物。 所述方法可以包括去除第一和第二牺牲膜图案。 所述方法可以包括修整第二间隔物，使得第二间隔物的线宽变得小于第一间隔物的线宽。 所述方法可以包括通过使用第一间隔物和修剪的第二间隔物作为蚀刻掩模蚀刻硬掩模膜来形成第一和第二硬掩模膜图案。