公开(公告)号：US20170345825A1

公开(公告)日：2017-11-30

申请号：US15680960

申请日：2017-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC: H01L27/11 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/762 ,  H01L27/092 ,  H01L27/088 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

公开(公告)号：US09305921B2

公开(公告)日：2016-04-05

申请号：US14565903

申请日：2014-12-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Chan Lee ,  Seung-Jae Lee ,  Sang-Bom Kang ,  Dae-Young Kwak ,  Myeong-Cheol Kim ,  Yong-Ho Jeon

IPC: H01L31/058 ,  H01L27/088 ,  H01L21/764 ,  H01L27/11 ,  H01L27/12

CPC classification number: H01L27/088 ,  H01L21/764 ,  H01L27/0886 ,  H01L27/1116 ,  H01L27/1211

Abstract: A semiconductor device including: a first gate pattern disposed in a peripheral region of a substrate; a second gate pattern disposed in a cell region of the substrate; a first insulator formed on sidewalls of the first gate pattern; and a second insulator formed on sidewalls of the second gate pattern, wherein a dielectric constant of the first insulator is different from a dielectric constant of the second insulator, and wherein a height of the second insulator is greater than a height of the second gate pattern.

Abstract translation: 一种半导体器件，包括：设置在衬底的周边区域中的第一栅极图案; 设置在所述基板的单元区域中的第二栅极图案; 形成在第一栅极图案的侧壁上的第一绝缘体; 以及形成在所述第二栅极图案的侧壁上的第二绝缘体，其中所述第一绝缘体的介电常数不同于所述第二绝缘体的介电常数，并且其中所述第二绝缘体的高度大于所述第二栅极图案的高度 。

公开(公告)号：US20150145056A1

公开(公告)日：2015-05-28

申请号：US14565903

申请日：2014-12-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Chan Lee ,  Seung-Jae Lee ,  Sang-Bom Kang ,  Dae-Young Kwak ,  Myeong-Cheol Kim ,  Yong-Ho Jeon

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L21/764 ,  H01L27/0886 ,  H01L27/1116 ,  H01L27/1211

Abstract: A semiconductor device including: a first gate pattern disposed in a peripheral region of a substrate; a second gate pattern disposed in a cell region of the substrate; a first insulator formed on sidewalls of the first gate pattern; and a second insulator formed on sidewalls of the second gate pattern, wherein a dielectric constant of the first insulator is different from a dielectric constant of the second insulator, and wherein a height of the second insulator is greater than a height of the second gate pattern.

Abstract translation: 一种半导体器件，包括：设置在衬底的周边区域中的第一栅极图案; 设置在所述基板的单元区域中的第二栅极图案; 形成在第一栅极图案的侧壁上的第一绝缘体; 以及形成在所述第二栅极图案的侧壁上的第二绝缘体，其中所述第一绝缘体的介电常数不同于所述第二绝缘体的介电常数，并且其中所述第二绝缘体的高度大于所述第二栅极图案的高度 。

公开(公告)号：US10522401B2

公开(公告)日：2019-12-31

申请号：US16237948

申请日：2019-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Myung ,  GeumJung Seong ,  Jisoo Oh ,  JinWook Lee ,  Dohyoung Kim ,  Yong-Ho Jeon

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66

Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.

公开(公告)号：US09947672B2

公开(公告)日：2018-04-17

申请号：US15371751

申请日：2016-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/11 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

公开(公告)号：US20170084617A1

公开(公告)日：2017-03-23

申请号：US15371751

申请日：2016-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC: H01L27/11 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

公开(公告)号：US10186457B2

公开(公告)日：2019-01-22

申请号：US15794107

申请日：2017-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Myung ,  GeumJung Seong ,  Jisoo Oh ,  JinWook Lee ,  Dohyoung Kim ,  Yong-Ho Jeon

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66

Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.

公开(公告)号：US20180374859A1

公开(公告)日：2018-12-27

申请号：US16115711

申请日：2018-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC: H01L27/11 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/78 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

公开(公告)号：US10096605B2

公开(公告)日：2018-10-09

申请号：US15680960

申请日：2017-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC: H01L29/06 ,  H01L27/11 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L21/762

Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

公开(公告)号：US11948844B2

公开(公告)日：2024-04-02

申请号：US17865040

申请日：2022-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Ho Jeon ,  Hyunwoo Choi ,  Se-Koo Kang ,  Miri Joung

IPC: H01L21/8238 ,  H01L21/033 ,  H01L21/308 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3086 ,  H01L27/0922 ,  H01L29/0642 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/7851

Abstract: Methods of fabricating semiconductor devices comprise forming first active patterns vertically spaced apart on a first active fin of a substrate and second active patterns vertically spaced apart on a second active fin of the substrate that has a first region on which the first active fin is formed and a second region on which the second active fin is formed, forming a first electrode layer on the first and second active fins and the first and second active patterns, forming a first mask pattern overlapping the first electrode layer on the first region, forming a second mask pattern overlapping the first electrode layer on the second region, and using the second mask pattern as an etching mask to etch the first mask pattern and the first electrode layer on the first region to form a first electrode pattern on the second region.