公开(公告)号：US09293343B2

公开(公告)日：2016-03-22

申请号：US14705969

申请日：2015-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do-Haing Lee ,  Il-Sup Kim ,  Do-Hyoung Kim ,  Woo-Cheol Lee ,  Hyun-Ho Jung

IPC: H01L21/44 ,  H01L21/308 ,  H01L21/768

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/76816

Abstract: A method of forming patterns of a semiconductor device includes forming a material film on a substrate, forming a hard mask on the material film, forming a first mold mask pattern and a second mold mask pattern on the hard mask, forming a pair of first spacers to cover opposite sidewalls of the first mold mask pattern, and a pair of second spacers to cover opposite sidewalls of the second mold mask pattern, forming a first gap and a second gap to expose the hard mask by removing the first mold mask pattern and the second mold mask pattern, the first gap being formed between the pair of first spacers and the second gap being formed between the pair of second spacers, forming a mask pattern on the hard mask to cover the first gap and expose the second gap, forming an auxiliary pattern to cover the second gap, removing the mask pattern; and forming a hard mask pattern by patterning the hard mask using the first spacers, the second spacers and the auxiliary pattern as a mask.

Abstract translation: 一种形成半导体器件的图案的方法包括：在基片上形成材料膜，在所述材料膜上形成硬掩模，在所述硬掩模上形成第一模具掩模图案和第二模具掩模图案，形成一对第一间隔物 以覆盖第一模具掩模图案的相对侧壁，以及一对第二间隔件，以覆盖第二模具掩模图案的相对的侧壁，形成第一间隙和第二间隙以通过去除第一模具掩模图案以暴露硬掩模，并且 第二模具掩模图案，所述第一间隙形成在所述一对第一间隔件和所述第二间隙之间，形成在所述一对第二间隔件之间，在所述硬掩模上形成掩模图案以覆盖所述第一间隙并暴露所述第二间隙， 辅助图案覆盖第二间隙，去除掩模图案; 以及通过使用第一间隔物，第二间隔物和辅助图案作为掩模来图案化硬掩模来形成硬掩模图案。

公开(公告)号：US20150076617A1

公开(公告)日：2015-03-19

申请号：US14548871

申请日：2014-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Cheol Kim ,  Il-Sup Kim ,  Cheol Kim ,  Jong-Chan Shin ,  Jong-Wook Lee ,  Choong-Ho Lee ,  Si-Young Choi ,  Jong-Seo Hong

IPC: H01L27/088 ,  H01L29/16

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/16

Abstract: Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.

Abstract translation: 提供了形成半导体器件的图案的方法。 所述方法可以包括在半导体衬底上形成硬掩模膜。 所述方法可以包括形成在硬掩模膜上彼此间隔开的第一和第二牺牲膜图案。 所述方法可以包括在第一牺牲膜图案的相对侧壁上形成第一间隔物，以及在第二牺牲膜图案的相对侧壁上形成第二间隔物。 所述方法可以包括去除第一和第二牺牲膜图案。 所述方法可以包括修整第二间隔物，使得第二间隔物的线宽变得小于第一间隔物的线宽。 所述方法可以包括通过使用第一间隔物和修剪的第二间隔物作为蚀刻掩模蚀刻硬掩模膜来形成第一和第二硬掩模膜图案。

公开(公告)号：US20130143372A1

公开(公告)日：2013-06-06

申请号：US13674386

申请日：2012-11-12

Applicant: Samsung Electronics Co., Ltd

Inventor： Myeong-Cheol KIM ,  Il-Sup Kim ,  Cheol Kim ,  Jong-Chan Shin ,  Jong-Wook Lee ,  Choong-Ho Lee ,  Si-Young Choi ,  Jong-Seo Hong

IPC: H01L21/308

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/16

Abstract: Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.

公开(公告)号：US09287161B2

公开(公告)日：2016-03-15

申请号：US14497501

申请日：2014-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hyun Lee ,  Myeong-Cheol Kim ,  Yoo-Jung Lee ,  Il-Sup Kim ,  Seung-Ju Park

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895

Abstract: A method of manufacturing a wiring includes sequentially forming a first insulation layer, a first layer, and a second layer on a substrate, etching an upper portion of the second layer a plurality of times to form a second layer pattern including a first recess having a shape of a staircase, etching a portion of the second layer pattern and a portion of the first layer under the first recess to form a first layer pattern including a second recess having a shape of a staircase similar to the first recess, etching a portion of the first layer pattern under the second recess to form a first opening exposing a portion of a top surface of the first insulation layer, etching the exposed portion of the first insulation layer to form a second opening through the first insulation layer, and forming a wiring filling the second opening.

Abstract translation: 一种制造布线的方法包括：在基板上依次形成第一绝缘层，第一层和第二层，多次蚀刻第二层的上部以形成第二层图案，该第二层图案包括具有第 形成阶梯，蚀刻第二层图案的一部分和在第一凹部下方的第一层的一部分，以形成第一层图案，该第一层图案包括具有类似于第一凹部的阶梯形状的第二凹部，蚀刻部分 在第二凹部下方的第一层图案，以形成暴露第一绝缘层的顶表面的一部分的第一开口，蚀刻第一绝缘层的暴露部分以形成穿过第一绝缘层的第二开口，以及形成布线 填补第二个开口。

公开(公告)号：US08906757B2

公开(公告)日：2014-12-09

申请号：US13674386

申请日：2012-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Cheol Kim ,  Il-Sup Kim ,  Cheol Kim ,  Jong-Chan Shin ,  Jong-Wook Lee ,  Choong-Ho Lee ,  Si-Young Choi ,  Jong-Seo Hong

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/308 ,  H01L21/033

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/16

Abstract: Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.

Abstract translation: 提供了形成半导体器件的图案的方法。 所述方法可以包括在半导体衬底上形成硬掩模膜。 所述方法可以包括形成在硬掩模膜上彼此间隔开的第一和第二牺牲膜图案。 所述方法可以包括在第一牺牲膜图案的相对侧壁上形成第一间隔物，以及在第二牺牲膜图案的相对侧壁上形成第二间隔物。 所述方法可以包括去除第一和第二牺牲膜图案。 所述方法可以包括修整第二间隔物，使得第二间隔物的线宽变得小于第一间隔物的线宽。 所述方法可以包括通过使用第一间隔物和修剪的第二间隔物作为蚀刻掩模蚀刻硬掩模膜来形成第一和第二硬掩模膜图案。