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公开(公告)号：US09299811B2
公开(公告)日：2016-03-29
申请号：US14519771
申请日：2014-10-21
发明人： Wook-Je Kim , Jae-Yup Chung , Jong-Seo Hong , Cheol Kim , Hee-Soo Kang , Hyun-Jo Kim , Hee-Don Jeong , Soo-Hun Hong , Sang-Bom Kang , Myeong-Cheol Kim , Young-Su Chung
IPC分类号： H01L29/66 , H01L21/8234 , H01L29/78 , H01L29/165
CPC分类号： H01L29/66795 , H01L21/823431 , H01L21/823481 , H01L29/165 , H01L29/66545 , H01L29/7848
摘要： Semiconductor devices may include first and second fins that protrude from a substrate, extend in a first direction, and are separated from each other in the first direction. Semiconductor devices may also include a field insulating layer that is disposed between the first and second fins to extend in a second direction intersecting the first direction, an etch-stop layer pattern that is formed on the field insulating layer and a dummy gate structure that is formed on the etch-stop layer pattern.
摘要翻译： 半导体器件可以包括从基板突出的第一和第二鳍片，沿第一方向延伸，并且在第一方向上彼此分离。 半导体器件还可以包括场绝缘层，其设置在第一和第二鳍之间，沿与第一方向相交的第二方向延伸，形成在场绝缘层上的蚀刻停止层图案和伪栅极结构， 形成在蚀刻停止层图案上。
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公开(公告)号：US20150147860A1
公开(公告)日：2015-05-28
申请号：US14519771
申请日：2014-10-21
发明人： Wook-Je Kim , Jae-Yup Chung , Jong-Seo Hong , Cheol Kim , Hee-Soo Kang , Hyun-Jo Kim , Hee-Don Jeong , Soo-Hun Hong , Sang-Bom Kang , Myeong-Cheol Kim , Young-Su Chung
IPC分类号： H01L29/66
CPC分类号： H01L29/66795 , H01L21/823431 , H01L21/823481 , H01L29/165 , H01L29/66545 , H01L29/7848
摘要： Semiconductor devices may include first and second fins that protrude from a substrate, extend in a first direction, and are separated from each other in the first direction. Semiconductor devices may also include a field insulating layer that is disposed between the first and second fins to extend in a second direction intersecting the first direction, an etch-stop layer pattern that is formed on the field insulating layer and a dummy gate structure that is formed on the etch-stop layer pattern.
摘要翻译： 半导体器件可以包括从基板突出的第一和第二鳍片，沿第一方向延伸，并且在第一方向上彼此分离。 半导体器件还可以包括场绝缘层，其设置在第一和第二鳍之间，沿与第一方向相交的第二方向延伸，形成在场绝缘层上的蚀刻停止层图案和伪栅极结构， 形成在蚀刻停止层图案上。
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公开(公告)号：US08906757B2
公开(公告)日：2014-12-09
申请号：US13674386
申请日：2012-11-12
发明人： Myeong-Cheol Kim , Il-Sup Kim , Cheol Kim , Jong-Chan Shin , Jong-Wook Lee , Choong-Ho Lee , Si-Young Choi , Jong-Seo Hong
IPC分类号： H01L21/00 , H01L21/84 , H01L21/308 , H01L21/033
CPC分类号： H01L27/0886 , H01L21/0337 , H01L21/3081 , H01L21/3086 , H01L29/16
摘要： Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.
摘要翻译： 提供了形成半导体器件的图案的方法。 所述方法可以包括在半导体衬底上形成硬掩模膜。 所述方法可以包括形成在硬掩模膜上彼此间隔开的第一和第二牺牲膜图案。 所述方法可以包括在第一牺牲膜图案的相对侧壁上形成第一间隔物，以及在第二牺牲膜图案的相对侧壁上形成第二间隔物。 所述方法可以包括去除第一和第二牺牲膜图案。 所述方法可以包括修整第二间隔物，使得第二间隔物的线宽变得小于第一间隔物的线宽。 所述方法可以包括通过使用第一间隔物和修剪的第二间隔物作为蚀刻掩模蚀刻硬掩模膜来形成第一和第二硬掩模膜图案。
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公开(公告)号：US09989856B2
公开(公告)日：2018-06-05
申请号：US15080706
申请日：2016-03-25
发明人： Jung-Woo Seo , Sang-Jin Kim , Jong-Seo Hong , Jong-Hoon Nah , Choon-Ho Song
IPC分类号： G03F7/20 , H01L29/66 , H01L21/033 , H01L21/311 , H01L21/3213
CPC分类号： G03F7/2022 , G03F7/2002 , H01L21/0334 , H01L21/31144 , H01L21/32139 , H01L29/66545 , H01L29/66795
摘要： Disclosed is a method of manufacturing semiconductor devices. A dummy gate structure is formed on a pattern area defined by an edge area of a substrate. An interlayer insulating layer pattern is formed to cover the pattern area and exposing the edge area of the substrate. A blocking pattern is formed on the interlayer insulating layer pattern such that the edge area of the substrate is covered with the blocking pattern and the pattern area of the substrate is exposed through the blocking pattern. A gate hole in the pattern area of the substrate in correspondence to the dummy gate structure, and a metal gate structure is formed in the gate hole. Accordingly, the edge area of the substrate is protected in the etching process and the deposition process of the replacement gate metal (RGM) process.
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公开(公告)号：US20150076617A1
公开(公告)日：2015-03-19
申请号：US14548871
申请日：2014-11-20
发明人： Myeong-Cheol Kim , Il-Sup Kim , Cheol Kim , Jong-Chan Shin , Jong-Wook Lee , Choong-Ho Lee , Si-Young Choi , Jong-Seo Hong
IPC分类号： H01L27/088 , H01L29/16
CPC分类号： H01L27/0886 , H01L21/0337 , H01L21/3081 , H01L21/3086 , H01L29/16
摘要： Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.
摘要翻译： 提供了形成半导体器件的图案的方法。 所述方法可以包括在半导体衬底上形成硬掩模膜。 所述方法可以包括形成在硬掩模膜上彼此间隔开的第一和第二牺牲膜图案。 所述方法可以包括在第一牺牲膜图案的相对侧壁上形成第一间隔物，以及在第二牺牲膜图案的相对侧壁上形成第二间隔物。 所述方法可以包括去除第一和第二牺牲膜图案。 所述方法可以包括修整第二间隔物，使得第二间隔物的线宽变得小于第一间隔物的线宽。 所述方法可以包括通过使用第一间隔物和修剪的第二间隔物作为蚀刻掩模蚀刻硬掩模膜来形成第一和第二硬掩模膜图案。
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公开(公告)号：US20130143372A1
公开(公告)日：2013-06-06
申请号：US13674386
申请日：2012-11-12
发明人： Myeong-Cheol KIM , Il-Sup Kim , Cheol Kim , Jong-Chan Shin , Jong-Wook Lee , Choong-Ho Lee , Si-Young Choi , Jong-Seo Hong
IPC分类号： H01L21/308
CPC分类号： H01L27/0886 , H01L21/0337 , H01L21/3081 , H01L21/3086 , H01L29/16
摘要： Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.
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