公开(公告)号：US09582224B2

公开(公告)日：2017-02-28

申请号：US14702768

申请日：2015-05-04

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Kuo-Hsin Lai ,  Tien-Ching Wang

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/34

CPC classification number: G06F3/0688 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G11C16/34

Abstract: A memory control circuit unit including a plurality of data randomizer circuits and a data selection circuit is provided. When a first data stream is received from a host system, the first data stream is input into the data randomizer circuits to respectively output a plurality of second data streams. The data selection circuit selects one of the second data streams as a third data stream according to contents of the second data streams, and the third data stream is programmed into a rewritable non-volatile memory module. Accordingly, data written into the rewritable non-volatile memory module can be effectively disarranged.

Abstract translation: 提供包括多个数据随机化器电路和数据选择电路的存储器控​​制电路单元。 当从主机系统接收到第一数据流时，将第一数据流输入到数据随机化器电路中，以分别输出多个第二数据流。 数据选择电路根据第二数据流的内容选择第二数据流中的一个作为第三数据流，并将第三数据流编程到可重写的非易失性存储器模块中。 因此，写入可重写非易失性存储器模块的数据可以被有效地排除。

公开(公告)号：US09529666B2

公开(公告)日：2016-12-27

申请号：US14295355

申请日：2014-06-04

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Shao-Wei Yen ,  Yu-Hsiang Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai ,  Siu-Tung Lam

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/42 ,  H03M13/37 ,  H03M13/00 ,  H03M13/11 ,  H03M13/15 ,  H03M13/23

CPC classification number: G06F11/1008 ,  G06F11/1012 ,  G11C29/42 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/152 ,  H03M13/23 ,  H03M13/3715 ,  H03M13/3723 ,  H03M13/6325

Abstract: A decoding method, a memory storage device and a memory controlling circuit are provided. The decoding method includes: sending a read command sequence configured to read the memory cells, so as to obtain a plurality of first verification bits; executing a first decoding procedure according to the first verification bits, and determining whether a first valid codeword is generated; if the first valid codeword is not generated, sending another read command sequence configured to obtain a plurality of second verification bits; calculating a total number of the memory cells conforming to a specific condition according to the second verification bits; obtaining a channel reliability message according to the total number; and executing a second decoding procedure according to the channel reliability message. Accordingly, a correcting ability of decoding may be improved.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路。 解码方法包括：发送配置为读取存储单元的读命令序列，以获得多个第一验证位; 执行根据所述第一验证比特的第一解码过程，以及确定是否生成第一有效码字; 如果不产生第一有效码字，则发送另一读取命令序列，被配置为获得多个第二验证比特; 根据第二验证位计算符合特定条件的存储单元的总数; 根据总数获取信道可靠性消息; 以及根据信道可靠性消息执行第二解码过程。 因此，可以提高解码的校正能力。

公开(公告)号：US20160247575A1

公开(公告)日：2016-08-25

申请号：US14682123

申请日：2015-04-09

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai

IPC: G11C16/26 ,  G11C29/52 ,  G06F11/10 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C16/26 ,  G06F11/1048 ,  G11C7/1006 ,  G11C2029/0411

Abstract: A data reading method is provided. The data reading method includes receiving a read command from a host system; sending a first read command sequence to obtain a first data string from memory cells of a rewritable non-volatile memory module; performing a decoding procedure on the first data string to generate a decoded first data string; and, if there is an error bit in the decoded first data string, sending a second read command sequence to obtain a second data string from the memory cells, performing a logical operation on the decoded first data string and the second data string to obtain an adjusting data string, adjusting the decoded first data string according to the adjusting data string to obtain an adjusted first data string, and using a data string obtained after re-performing the decoding procedure on the adjusted first data string as the decoded first data string.

Abstract translation: 提供了一种数据读取方法。 数据读取方法包括从主机系统接收读取命令; 发送第一读取命令序列以从可重写非易失性存储器模块的存储器单元获得第一数据串; 对所述第一数据串执行解码过程以生成解码的第一数据串; 并且如果在解码的第一数据串中存在错误位，则从存储器单元发送第二读取命令序列以获得第二数据串，对解码的第一数据串和第二数据串执行逻辑运算以获得 调整数据串，根据调整数据串调整解码后的第一数据串，得到经调整后的第一数据串，并使用对经过调整的第一数据串进行解码过程后获得的数据串作为解码后的第一数据串。

公开(公告)号：US20150095741A1

公开(公告)日：2015-04-02

申请号：US14109959

申请日：2013-12-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Shao-Wei Yen ,  Yu-Hsiang Lin ,  Kuo-Hsin Lai ,  Kuo-Yi Cheng

IPC: G06F11/10

CPC classification number: G06F11/1008 ,  G06F11/1048

Abstract: A decoding method, a memory storage device and a memory controlling circuit unit are provided. The method includes: reading memory cells according to a first reading voltage to obtain first verifying bits; executing a decoding procedure including a probability decoding algorithm according to the first verifying bits to obtain first decoded bits, and determining whether a decoding is successful by using the decoded bits; if the decoding is failed, reading the memory cells according to a second reading voltage to obtain second verifying bits, and executing the decoding procedure according to the second verifying bits to obtain second decoded bits. The second reading voltage is different from the first reading voltage, and the number of the second reading voltage is equal to the number of the first reading voltage. Accordingly, the ability for correcting errors is improved.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路单元。 该方法包括：根据第一读取电压读取存储器单元以获得第一验证位; 执行包括根据第一验证位的概率解码算法的解码过程以获得第一解码比特，并且通过使用解码比特来确定解码是否成功; 如果解码失败，则根据第二读取电压读取存储器单元以获得第二验证位，并且根据第二验证位执行解码过程以获得第二解码位。 第二读取电压与第一读取电压不同，第二读取电压的数量等于第一读取电压的数量。 因此，能够提高校正误差的能力。

公开(公告)号：US20140047300A1

公开(公告)日：2014-02-13

申请号：US13662541

申请日：2012-10-28

Applicant: PHISON ELECTRONICS CORP.

Inventor： Li-Chun Liang ,  Tien-Ching Wang ,  Kuo-Hsin Lai

IPC: H03M13/13

CPC classification number: G06F11/1008 ,  G06F11/1044 ,  G06F11/1068 ,  G11C7/1006 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/19 ,  H03M13/271 ,  H03M13/2778 ,  H03M13/2906

Abstract: A data processing method adapted for a rewritable non-volatile memory module is provided. The method includes receiving a first data stream and performing an error-correction encoding procedure on the first data stream to generate an original error checking and correcting (ECC) code corresponding to the first data stream. The method also includes converting the original ECC code into a second ECC code according to a second rearrangement rule, and the original ECC code is different from the second ECC code. The method further includes respectively writing the first data stream and the second ECC code into a data bit area and an error-correction code bit area of the same or different physical programming units in the rewritable non-volatile memory module.

Abstract translation: 提供了一种适用于可重写非易失性存储器模块的数据处理方法。 该方法包括接收第一数据流并对第一数据流执行纠错编码过程以产生对应于第一数据流的原始错误校验和校正（ECC）代码。 该方法还包括根据第二重排规则将原始ECC码转换成第二ECC码，并且原始ECC码与第二ECC码不同。 该方法还包括分别将第一数据流和第二ECC码写入可重写非易失性存储器模块中相同或不同的物理编程单元的数据位区和纠错码位区。

公开(公告)号：US20190114227A1

公开(公告)日：2019-04-18

申请号：US15831405

申请日：2017-12-05

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Hsiang Lin ,  Shao-Wei Yen ,  Yu-Siang Yang ,  Kuo-Hsin Lai

IPC: G06F11/10 ,  G11C29/52

Abstract: A decoding method is provided according to an exemplary embodiment of the invention. The decoding method includes: reading a data set from at least two physical units of a rewritable non-volatile memory module by using at least one read voltage level; performing a first-type decoding operation for first data by using the data set and recording decoding information of the first-type decoding operation if the data set conforms to a default condition; adjusting reliability information corresponding to the first data according to the recorded decoding information, and the reliability information is not used in the first-type decoding operation, and the adjusted reliability information is different from default reliability information corresponding to the first data; and performing a second-type decoding operation for the first data according to the adjusted reliability information.

公开(公告)号：US09639419B2

公开(公告)日：2017-05-02

申请号：US14745472

申请日：2015-06-22

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai

IPC: H03M13/09 ,  G06F11/10 ,  G11C29/02 ,  G11C29/44 ,  G11C29/50

CPC classification number: G06F11/1048 ,  G11C29/021 ,  G11C29/028 ,  G11C29/44 ,  G11C2029/5004

Abstract: A read voltage level estimating method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a first region of a rewritable non-volatile memory module according to a first read voltage level to obtain a first encoding unit which belongs to a block code; performing a first decoding procedure on the first encoding unit and recording first decoding information; reading the first region according to a second read voltage level to obtain a second encoding unit which belongs to the block code; performing a second decoding procedure on the second encoding unit and recording second decoding information; and estimating and obtaining a third read voltage level according to the first decoding information and the second decoding information. Accordingly, a management ability of the rewritable non-volatile memory module adopting the block code may be improved.

公开(公告)号：US09607704B2

公开(公告)日：2017-03-28

申请号：US14682123

申请日：2015-04-09

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai

IPC: G11C29/00 ,  G11C16/26 ,  G06F11/10 ,  G11C7/10 ,  G11C29/04

CPC classification number: G11C16/26 ,  G06F11/1048 ,  G11C7/1006 ,  G11C2029/0411

Abstract: A data reading method is provided. The data reading method includes receiving a read command from a host system; sending a first read command sequence to obtain a first data string from memory cells of a rewritable non-volatile memory module; performing a decoding procedure on the first data string to generate a decoded first data string; and, if there is an error bit in the decoded first data string, sending a second read command sequence to obtain a second data string from the memory cells, performing a logical operation on the decoded first data string and the second data string to obtain an adjusting data string, adjusting the decoded first data string according to the adjusting data string to obtain an adjusted first data string, and using a data string obtained after re-performing the decoding procedure on the adjusted first data string as the decoded first data string.

公开(公告)号：US09530509B2

公开(公告)日：2016-12-27

申请号：US14727878

申请日：2015-06-02

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai ,  Yu-Cheng Hsu ,  Chi-Heng Yang

IPC: G06F12/00 ,  G11C16/14 ,  G06F3/06 ,  G06F12/08 ,  G11C16/26 ,  G11C29/44

CPC classification number: G11C16/14 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0802 ,  G06F2212/1044 ,  G06F2212/7203 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/4401 ,  G11C2029/0409 ,  G11C2211/5648

Abstract: A data programming method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving first data and programming the first data into a first lower physical programming unit; receiving second data; in response to the second data to be programmed into a first upper physical programming unit corresponding to the first lower physical programming unit, performing a first data obtaining operation which does not include reading the first lower physical programming unit by using a default read voltage; and programming the second data into the first upper physical programming unit according to the third data obtained through the first data obtaining operation.

Abstract translation: 提供数据编程方法，存储器存储装置和存储器控制电路单元。 该方法包括：接收第一数据并将第一数据编程到第一较低物理编程单元中; 接收第二数据; 响应于要被编程到与第一下部物理编程单元相对应的第一上部物理编程单元的第二数据，执行不包括通过使用默认读取电压读取第一下部物理编程单元的第一数据获取操作; 以及根据通过第一数据获取操作获得的第三数据将第二数据编程到第一上层物理编程单元中。

公开(公告)号：US09431132B2

公开(公告)日：2016-08-30

申请号：US14307509

申请日：2014-06-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Li-Chun Liang ,  Kuo-Hsin Lai ,  Pei-Yu Shih ,  Tien-Ching Wang

IPC: G11C29/00 ,  G11C29/52 ,  G06F11/10 ,  G11B20/18 ,  G11C29/04

CPC classification number: G11C29/52 ,  G06F11/1012 ,  G06F11/106 ,  G06F11/1068 ,  G06F11/1076 ,  G11B20/1833 ,  G11C2029/0411

Abstract: A data managing method, and a memory control circuit unit and a memory storage apparatus using the same are provided. The data managing method including: reading a first data stream from a first physical erasing unit according to a first reading command, wherein the first data stream includes first user data, a first error correcting code and a first error detecting code. The method also includes: using the first error correcting code and error detecting code to decode the first user data and determining whether the first user data is decoded successfully. The method further includes: if the first user data is decoded successfully, transmitting corrected user data obtained by correctly decoding the first user data to the host system in response to the first reading command.

Abstract translation: 提供数据管理方法，以及存储器控制电路单元和使用该数据管理方法的存储器存储装置。 所述数据管理方法包括：根据第一读取命令从第一物理擦除单元读取第一数据流，其中所述第一数据流包括第一用户数据，第一纠错码和第一错误检测码。 该方法还包括：使用第一纠错码和错误检测码对第一用户数据进行解码，并确定第一用户数据是否被成功解码。 该方法还包括：如果第一用户数据被成功解码，则响应于第一读取命令，将通过将第一用户数据正确解码而获得的校正用户数据发送给主机系统。