公开(公告)号：US20150262968A1

公开(公告)日：2015-09-17

申请号：US14727205

申请日：2015-06-01

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Ravindranath V Mahajan ,  Omkar Karhade ,  Nitin Deshpande

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/677

CPC classification number: H01L24/83 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/67709 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/15 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L2221/68309 ,  H01L2221/68313 ,  H01L2221/68331 ,  H01L2221/68363 ,  H01L2224/04105 ,  H01L2224/2101 ,  H01L2224/2919 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/8312 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The subject matter of the present description relates to methods for the precise integration of microelectronic dice within a multichip package which substantially reduce or eliminate any misalign caused by the movement of the microelectronic dice during the integration process. These methods may include the use of a temporary adhesive in conjunction with a carrier having at least one recess for microelectronic die alignment, the use of a precision molded carrier for microelectronic die alignment, the use of magnetic alignment of microelectronic dice on a reusable carrier, and/or the use of a temporary adhesive with molding processes on a reusable carrier.

Abstract translation: 本说明书的主题涉及用于在多芯片封装内精确地集成微电子管芯的方法，其基本上减少或消除了在整合过程期间由微电子管芯的移动引起的任何不对准。 这些方法可以包括使用临时粘合剂与具有用于微电子管芯对准的至少一个凹部的载体的使用，使用用于微电子管芯对准的精密模制载体，在可重复使用的载体上使用微电子骰子的磁对准， 和/或在可重复使用的载体上使用具有模制工艺的临时粘合剂。

公开(公告)号：US09076882B2

公开(公告)日：2015-07-07

申请号：US13908016

申请日：2013-06-03

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Ravindranath V Mahajan ,  Omkar Karhade ,  Nitin Deshpande

IPC: H01L21/00 ,  H01L23/00

CPC classification number: H01L24/83 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/67709 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/15 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L2221/68309 ,  H01L2221/68313 ,  H01L2221/68331 ,  H01L2221/68363 ,  H01L2224/04105 ,  H01L2224/2101 ,  H01L2224/2919 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/8312 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The subject matter of the present description relates to methods for the precise integration of microelectronic dice within a multichip package which substantially reduce or eliminate any misalign caused by the movement of the microelectronic dice during the integration process. These methods may include the use of a temporary adhesive in conjunction with a carrier having at least one recess for microelectronic die alignment, the use of a precision molded carrier for microelectronic die alignment, the use of magnetic alignment of microelectronic dice on a reusable carrier, and/or the use of a temporary adhesive with molding processes on a reusable carrier.

Abstract translation: 本说明书的主题涉及用于在多芯片封装内精确地集成微电子管芯的方法，其基本上减少或消除了在整合过程期间由微电子管芯的移动引起的任何不对准。 这些方法可以包括使用临时粘合剂与具有用于微电子管芯对准的至少一个凹部的载体的使用，使用用于微电子管芯对准的精密模制载体，在可重复使用的载体上使用微电子骰子的磁对准， 和/或在可重复使用的载体上使用具有模制工艺的临时粘合剂。

公开(公告)号：US12174436B2

公开(公告)日：2024-12-24

申请号：US17214035

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Wesley Morgan ,  Srikant Nekkanty ,  Todd R. Coons ,  Gregorio R. Murtagian ,  Xiaoqian Li ,  Nitin Deshpande ,  Divya Pratap

IPC: H04B10/00 ,  G02B6/42

Abstract: Embodiments disclosed herein include photonics packages and systems. In an embodiment, a photonics package comprises a package substrate, where the package substrate comprises a cutout along an edge of the package substrate. In an embodiment, a photonics die is coupled to the package substrate, and the photonics die is positioned adjacent to the cutout. In an embodiment, the photonics package further comprises a receptacle for receiving a pluggable optical connector. In an embodiment, the receptacle is over the cutout.

公开(公告)号：US20230207525A1

公开(公告)日：2023-06-29

申请号：US17561845

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Sriram Srinivasan ,  Christopher Pelto ,  Gwang-Soo Kim ,  Nitin Deshpande ,  Omkar Karhade

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3185 ,  H01L24/08 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/73253 ,  H01L2225/06568

Abstract: A packaged device comprises first die stack and a third die. The first die stack includes a first die comprising first conductive contacts each at a first side of the first die, and a second die comprising second conductive contacts each at a second side of the second die. First solder bonds which each extend to a respective one of the first conductive contacts. The third die comprises third conductive contacts each at a third side of the third die. The third die is coupled to the first die stack via second solder bonds which each extend to a respective one of the second conductive contacts, and to a respective one of the third conductive contacts. Each die of the first die stack is coupled to each of a respective one or more other dies of the first die stack via respective hybrid bonds.

公开(公告)号：US20200273768A1

公开(公告)日：2020-08-27

申请号：US16287668

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal ,  Debendra Mallik ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Kumar Singh

IPC: H01L23/31 ,  H01L23/532 ,  H01L23/34 ,  H01L23/00 ,  H01L21/56

Abstract: IC packages including a heat spreading material comprising crystalline carbon. The heat spreading material may be applied directly to an IC die surface, for example at a die prep stage, prior to an application or build-up of packaging material, so that the high thermal conductivity may best mitigate any hot spots that develop at the IC die surface during operation. The heat spreading material may be applied to surface of the IC die.

公开(公告)号：US20190104610A1

公开(公告)日：2019-04-04

申请号：US15720488

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Robert Nickerson ,  Nitin Deshpande ,  Omkar Karhade ,  Thomas De Bonis

IPC: H05K1/02 ,  H05K1/14 ,  H05K3/00

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a first substrate comprising a first die, wherein an underfill material is disposed on a first surface of the first substrate adjacent the first die; and a second substrate disposed on the first substrate, wherein the second substrate comprises at least one opening disposed over the first die, wherein the at least one opening is at least partially filled with the underfill material.

公开(公告)号：US09991243B2

公开(公告)日：2018-06-05

申请号：US15437237

申请日：2017-02-20

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Nitin Deshpande ,  Bassam M. Ziadeh ,  Yoshihiro Tomita

IPC: H01L23/48 ,  H01L25/18 ,  H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/26155 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49109 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/81203 ,  H01L2224/83 ,  H01L2224/83851 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2225/06593 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/19104 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/45099

Abstract: An integrated circuit assembly that includes a substrate; a member formed on the substrate; a first die mounted to the substrate within an opening in the member such that there is space between the first die and the member and the member surrounds the first die, and wherein the first die does not extend above an upper surface of the member; an underfill between the first the die and the substrate, wherein the underfill at least partially fills the space between the die and member; and a second die mounted to the first die and the member, wherein the second die is mounted to the member on all sides of the opening.

公开(公告)号：US09795038B2

公开(公告)日：2017-10-17

申请号：US14496560

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Nitin Deshpande ,  Nachiket Raravikar

IPC: H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H05K3/30 ,  H01L23/00

CPC classification number: H05K3/305 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K2201/10734 ,  H05K2203/0191 ,  Y02P70/613 ,  H01L2924/00

Abstract: Some example forms relate to an electronic package. The electronic package includes an electronic component and a substrate that includes a front side and a back side. The electronic component is mounted on the front side of the substrate and conductors are mounted on the back side of the substrate. The substrate is warped due to differences in the coefficients of thermal expansion between the electronic component and the substrate. An adhesive is positioned between the conductors on the back side of the substrate and an adhesive film is attached to the adhesive positioned between the conductors on the back side of the substrate.

公开(公告)号：US20230207545A1

公开(公告)日：2023-06-29

申请号：US17561832

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Omkar Karhade ,  Nitin Deshpande

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L25/18 ,  H01L24/13 ,  H01L23/3185 ,  H01L23/481 ,  H01L2224/13147 ,  H01L2924/014

Abstract: An integrated circuit (IC) package comprises a first IC die comprising a first hardware interface at a first side of the first die, and one or more first conductive contacts at the first side. A second IC die coupled to the first die comprises a second hardware interface at a second side of the second die. Second conductive contacts of the first hardware interface are each in direct contact with a respective one of third conductive contacts of the second hardware interface. A third hardware interface comprises: one or more interconnect structures, each coupled to a respective one of the one or more first conductive contacts and each comprising a fourth conductive contact, and fifth conductive contacts at a third side of the second die, wherein the one or more interconnect structures are each to electrically couple the third hardware interface to the first die.

公开(公告)号：US20230207471A1

公开(公告)日：2023-06-29

申请号：US17560609

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Omkar Karhade ,  Nitin Deshpande

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/5383 ,  H01L25/0655 ,  H01L23/481 ,  H01L24/08 ,  H01L25/50 ,  H01L24/80 ,  H01L2224/08235 ,  H01L2224/80815 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/16225

Abstract: Multi-die composite packages including directly bonded IC die and at least one electro-thermo-mechanical die (ETMD). An ETMD is distinguished from an active IC die as an ETMD is a passive die lacking any semiconductor devices, such as transistors. In exemplary embodiments, an ETMD includes a substrate, which may be a crystalline semiconductor material, for example, and one or more through substrate vias (TSVs) passing through a thickness of the substrate. The TSVs may enable a ETMD to electrically interconnect an (active) IC die of a composite package to another IC die of the package or to a package host.