公开(公告)号：US10228418B2

公开(公告)日：2019-03-12

申请号：US15126988

申请日：2014-04-21

Applicant: INTEL CORPORATION

Inventor： Sruti Chigullapalli ,  Rene J. Sanchez ,  Nader N. Abazarnia ,  Todd R. Coons ,  Tuan Hoong Goh

IPC: G01R31/28 ,  G01R1/04

Abstract: Embodiments of alignment fixtures for integrated circuit (IC) packages, and related techniques, are disclosed herein. In some embodiments, an alignment fixture for an IC package may include: a first socket having a recess dimensioned to receive a first surface of the IC package and having a first magnet arrangement disposed outside of the recess, wherein the IC package has a second surface opposite to the first surface and has a first electrical contact element on the second surface; and a second socket having a second electrical contact element and having a second magnet arrangement. The first and second electrical contact elements may be aligned when the IC package is disposed in the recess, the IC package is disposed between the first and second sockets, and the first magnet arrangement is in a predetermined equilibrium relation with the second magnet arrangement to mate the first and second sockets.

公开(公告)号：US12061230B2

公开(公告)日：2024-08-13

申请号：US17131604

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Todd R. Coons ,  Michael Rutigliano ,  Joe F. Walczyk ,  Abram M. Detofsky

IPC: G01R31/308 ,  G02B6/42

CPC classification number: G01R31/308 ,  G02B6/4256 ,  G02B6/4292

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to active optical plugs used to cover optical connectors of a photonics package to protect the connectors. The active optical plugs may also be used to perform testing of the photonics package, including generating light to be sent to the photonics package and to detect light received from the photonics package as part of the test protocol. This allows testing the optical connection and the photonics package, without exposing the optical connections of the package to damage from dust or physical contact. Other embodiments may be described and/or claimed.

公开(公告)号：US12174436B2

公开(公告)日：2024-12-24

申请号：US17214035

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Wesley Morgan ,  Srikant Nekkanty ,  Todd R. Coons ,  Gregorio R. Murtagian ,  Xiaoqian Li ,  Nitin Deshpande ,  Divya Pratap

IPC: H04B10/00 ,  G02B6/42

Abstract: Embodiments disclosed herein include photonics packages and systems. In an embodiment, a photonics package comprises a package substrate, where the package substrate comprises a cutout along an edge of the package substrate. In an embodiment, a photonics die is coupled to the package substrate, and the photonics die is positioned adjacent to the cutout. In an embodiment, the photonics package further comprises a receptacle for receiving a pluggable optical connector. In an embodiment, the receptacle is over the cutout.

公开(公告)号：US12135460B2

公开(公告)日：2024-11-05

申请号：US17132912

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Todd R. Coons ,  Michael Rutigliano ,  Joe F. Walczyk ,  Abram M. Detofsky

IPC: G02B6/42 ,  G02B6/12 ,  G02B6/30 ,  G02B6/34 ,  H01L25/075 ,  H01L33/58 ,  H01L33/62 ,  H01L23/367 ,  H04B10/40

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to incorporating photonics integrated circuitry into a base die, the base die including an optical interconnect at a bottom of the base die to transmit and to receive light signals from outside the base die. The top of the base die includes one or more electrical connectors that are electrically coupled with the photonics integrated circuitry. The base die may be referred to as the photonics die. A system-on-a-chip (SOC) may be electrically coupled with and stacked onto the top of the photonics die. Other embodiments may be described and/or claimed.