公开(公告)号：US20020137322A1

公开(公告)日：2002-09-26

申请号：US10094835

申请日：2002-03-07

Applicant: International Rectifier Corp.

Inventor： Kyle Spring ,  Jianjun Cao

IPC: H01L021/44 ,  H01L021/3205 ,  H01L021/4763 ,  H01L021/332 ,  H01L031/119 ,  H01L031/062 ,  H01L031/113 ,  H01L029/94 ,  H01L029/76

CPC classification number: H01L29/66719 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/66712 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process for forming a power MOSFET enables the connection a metal gate electrode to the conductive polysilicon gates in the active area without an additional mask step. In the process, a groove is formed in the field oxide during the active area mask step. Conductive polysilicon is then formed over the active area and into the groove. At least one window is formed over the groove along with the mask window for forming the channel and source implant windows, and the polysilicon is etched to the silicon surface in the active area, but a strip is left in the groove. This strip is contacted by gate metal during metal deposition. Thus, gate metal is connected to the polysilicon without an added mask step.

Abstract translation: 用于形成功率MOSFET的工艺使得能够在没有额外的掩模步骤的情况下将金属栅电极连接到有源区中的导电多晶硅栅极。 在该过程中，在有源区掩模步骤期间，在场氧化物中形成凹槽。 然后在有源区域上形成导电多晶硅并进入沟槽。 至少一个窗口与用于形成沟道和源植入窗口的掩模窗口一起形成在沟槽上方，并且多晶硅被蚀刻到有源区域中的硅表面，但是条带留在沟槽中。 在金属沉积期间，该带与栅极金属接触。 因此，栅极金属连接到多晶硅而没有添加掩模步骤。

公开(公告)号：US20020132456A1

公开(公告)日：2002-09-19

申请号：US10082532

申请日：2002-02-21

Applicant: International Rectifier Corp.

Inventor： Hamilton Lu

IPC: H01L021/28

CPC classification number: H01L21/324 ,  H01L21/28061 ,  H01L29/4933

Abstract: A single rapid thermal anneal (RTA) process is used to form a low resistivity titanium silicide layer atop a polysilicon gate layer for a MOSgated device. The process employs an amorphous silicon layer formed atop the polysilicon layer, followed by forming a titanium layer atop the amorphous silicon. A single RTA process at a temperature below the temperature of contamination diffusion is carried out, preferably at about 650null C. for 30 seconds. The top of the annealed titanium silicide layer is then stripped, and the remaining layer has a sheet Rho of less than about 2 ohms per square.

Abstract translation: 使用单个快速热退火（RTA）工艺在MOS多晶硅栅极层的顶部形成用于MOS器件的低电阻率硅化钛层。 该方法使用形成在多晶硅层顶上的非晶硅层，随后在非晶硅顶上形成钛层。 在低于污染扩散温度的温度下进行单个RTA方法，优选在约650℃下进行30秒。 然后剥离退火的硅化钛层的顶部，剩余的层具有小于约2欧姆/平方的片材Rho。

公开(公告)号：US20020008246A1

公开(公告)日：2002-01-24

申请号：US09862017

申请日：2001-05-21

Applicant: International Rectifier Corp.

Inventor： Richard Francis ,  Chiu Ng

IPC: H01L029/861

CPC classification number: H01L29/66136 ,  H01L29/0619 ,  H01L29/32 ,  H01L29/872 ,  Y10S257/91

Abstract: A soft recovery diode is made by first implanting helium into the die to a location below the P/N junction and the implant annealed. An E-beam radiation process then is applied to the entire wafer and is also annealed. The diode then has very soft recovery characteristics without requiring heavy metal doping.

Abstract translation: 软恢复二极管通过首先将氦注入管芯到位于P / N结下方的位置并进行退火而制成。 然后将电子束辐射过程施加到整个晶片并且也被退火。 二极管然后具有非常柔软的恢复特性，而不需要重金属掺杂。

公开(公告)号：US20010048116A1

公开(公告)日：2001-12-06

申请号：US09819774

申请日：2001-03-28

Applicant: International Rectifier Corp.

Inventor： Martin Standing ,  Hazel D. Schofield

IPC: H01L029/74 ,  H01L021/44

CPC classification number: H01L23/492 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/544 ,  H01L24/81 ,  H01L24/83 ,  H01L2223/54486 ,  H01L2224/1147 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/73153 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83851 ,  H01L2924/01004 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/3025 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.

Abstract translation: 芯片级封装具有半导体MOSFET管芯，其具有覆盖有感光性液体环氧树脂层的顶部电极表面，该层被光刻图案化以暴露电极表面的部分并且用作钝化层和作为焊接掩模。 然后在钝化层上形成可焊接接触层。 单个管芯的排水侧面向下安装在金属夹子或罐中，其中漏电极设置为与罐底部延伸的凸缘共面。

公开(公告)号：US20010046145A1

公开(公告)日：2001-11-29

申请号：US09814237

申请日：2001-03-21

Applicant: International Rectifier Corp.

Inventor： V. Stepan Oknaian ,  J. Steven Brown

IPC: H02M003/24

CPC classification number: H02M3/156 ,  H01L2924/19043 ,  H02M3/1588 ,  H02M2001/0009 ,  Y02B70/1466

Abstract: A circuit and method for sensing the inductor current flowing to a load from a switching power supply without using a sense resistor in the path of the inductor current. In a synchronous buck converter topology, the inductor current is derived by sensing the voltage drop across the synchronous MOSFET of the half-bridge and reconstructing the current using a sample and hold technique. A ripple current synthesizer is employed to reconstruct inductor current outside the sample and hold window. The sampled product ILoadnullRDSon is used to update the ripple current estimator with dc information every switching cycle. The resulting voltage waveform is directly proportional to the inductor current. The inductor current synthesizer of the present invention can also be used in boost converter, flyback converter and forward converter topologies.

Abstract translation: 一种用于感测从开关电源流向负载的电感器电流而不在电感器电流的路径中使用检测电阻器的电路和方法。 在同步降压转换器拓扑中，通过感测半桥的同步MOSFET上的电压降并通过采样和保持技术来重建电流来导出电感电流。 纹波电流合成器用于重建样品和保持窗外的电感电流。 采样产品ILoadxRDSon用于每个切换周期用直流信息更新纹波电流估计器。 所产生的电压波形与电感电流成正比。 本发明的电感器电流合成器也可用于升压转换器，反激转换器和正激转换器拓扑。

公开(公告)号：US20010033022A1

公开(公告)日：2001-10-25

申请号：US09782245

申请日：2001-02-13

Applicant: International Rectifier Corp.

Inventor： Peter R. Ewer

IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: H01L23/4951 ,  H01L23/34 ,  H01L23/49582 ,  H01L24/34 ,  H01L24/37 ,  H01L24/45 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/3716 ,  H01L2224/3754 ,  H01L2224/45124 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/10253 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/48

Abstract: A contact clip for the aluminum contact of a semiconductor device has a central nickel-iron body, preferably Nilo alloy 42, which is coated on top and bottom by a soft, but high conductivity metal such as gold, silver or copper. The nickel-iron body has a thickness of about 15 mils, and is about the thickness of the silicon die. The conductive layers have a thickness of about 5% to 20% of that of the nickel-iron core.

Abstract translation: 用于半导体器件的铝触点的接触夹具有中心镍铁体，优选Nilo合金42，其通过软的但高导电性的金属（例如金，银或铜）涂覆在顶部和底部。 镍铁体的厚度约为15密耳，约为硅模的厚度。 导电层的厚度约为镍铁芯的约5％至20％。

公开(公告)号：US20040007723A1

公开(公告)日：2004-01-15

申请号：US10193783

申请日：2002-07-11

Applicant: International Rectifier Corp.

Inventor： Kohji Andoh ,  Davide Chiola

IPC: H01L029/80 ,  H01L027/095 ,  H01L029/47

CPC classification number: H01L29/407 ,  H01L27/0814 ,  H01L29/66143 ,  H01L29/8725 ,  Y10S438/963

Abstract: A fabrication process for a Schottky barrier structure includes forming a nitride layer directly on a surface of an epitaxial (nullepinull) layer and subsequently forming a plurality of trenches in the epi layer. The interior walls of the trenches are then deposited with a final oxide layer without forming a sacrificial oxide layer to avoid formation of a beak bird at the tops of the interior trench walls. A termination trench is etched in the same process step for forming the plurality of trenches in the active area.

Abstract translation: 用于肖特基势垒结构的制造方法包括在外延（“epi”）层的表面上直接形成氮化物层，随后在外延层中形成多个沟槽。 然后将沟槽的内壁沉积有最终的氧化物层，而不形成牺牲氧化物层，以避免在内部沟槽壁的顶部形成喙鸟。 在用于在有源区域中形成多个沟槽的相同工艺步骤中蚀刻端接沟槽。

公开(公告)号：US20030201454A1

公开(公告)日：2003-10-30

申请号：US10132549

申请日：2002-04-25

Applicant: International Rectifier Corp.

Inventor： Richard Francis ,  Chiu Ng

IPC: H01L029/74

CPC classification number: H01L29/7397 ,  H01L29/0834 ,  H01L29/1095

Abstract: An IGBT has parallel spaced trenches lined with gate oxide and filled with conductive polysilicon gate bodies. The trenches extend through a Pnull base region which is about 7 microns deep. A deep narrow Nnull emitter diffusion is at the top of the trench and a shallow Pnull contact diffusion extends between adjacent emitter diffusions. The Nnull emitter diffusions are arranged to define a minimum RBnull. The trenches are sufficiently deep to define long channel regions which can withstand a substantial portion of the blocking voltage of the device. A second blanket emitter implant and diffusion defines a shallow high concentration emitter diffusion extension at the top of the die for improved contact to the emitter diffusions.

Abstract translation: IGBT具有与栅极氧化物排列并且填充有导电多晶硅栅极体的平行隔开的沟槽。 沟槽延伸穿过大约7微米深的P'基底区域。 深沟N +发射体扩散在沟槽的顶部，浅的P +接触扩散在相邻的发射极扩散之间延伸。 N +发射极扩散布置成限定最小RB'。 沟槽足够深以限定可以承受器件的大部分阻断电压的长通道区域。 第二个覆盖发射器的注入和扩散在芯片的顶部限定了一个浅的高浓度发射极扩散延伸，以改善与发射极扩散的接触。

公开(公告)号：US20020047198A1

公开(公告)日：2002-04-25

申请号：US10002252

申请日：2001-10-26

Applicant: International Rectifier Corp.

Inventor： Tim Sammon

IPC: H01L023/48

CPC classification number: H01L23/49562 ,  H01L23/49503 ,  H01L2224/291 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Semiconductor die are soldered or epoxy bonded to lead frame pads and overhang the pads to reduce thermal differential expansion and contraction stresses applied to the die from the lead frame pad. A plastic housing of standard size is unchanged in dimension, but contains a greater total silicon die area.

Abstract translation: 将半导体管芯焊接或环氧接合到引线框架焊盘并且悬垂焊盘以减少从引线框架焊盘施加到管芯的热差异膨胀和收缩应力。 标准尺寸的塑料外壳的尺寸不变，但是包含更大的总硅芯片面积。

公开(公告)号：US20010050441A1

公开(公告)日：2001-12-13

申请号：US09812027

申请日：2001-03-19

Applicant: International Rectifier Corp.

Inventor： Bharat Shivkumar ,  Chuan Cheah

IPC: H01L023/48 ,  H01L023/52

CPC classification number: H01L23/564 ,  H01L21/563 ,  H01L23/24 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3737 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/12044 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1515 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A multichip module has a substrate, which receives several flip chip and for other semiconductor die on one surface and has vias extending through the substrate from the flip chip bottom electrodes to solder ball electrodes on the bottom of the substrate. Passive components are also mounted on the top of the substrate and are connected to further vias which extend to respective ball contacts at the substrate bottom. In one embodiment, the bottom surfaces and electrodes of the die are insulated and their tops (and drain electrodes) are connected by a moldable conductive layer. In another embodiment the top surface of the substrate is covered by an insulation cap, which may be finned for improved thermal properties. The passives are upended to have their longest dimension perpendicular to the substrate surface and are between the fin valleys. The insulation cover is a cap which fits over the top of the substrate, with mold lock depressions contained in the junction between the cap peripheral interior edge and the substrate mating edge surfaces.

Abstract translation: 多芯片模块具有基板，其在一个表面上接收多个倒装芯片和其它半导体管芯，并且具有从倒装芯片底部电极延伸穿过基板的通孔到基板底部的焊球电极。 被动元件也安装在基板的顶部，并且连接到在基板底部延伸到相应的滚珠触点的另外的通孔。 在一个实施例中，管芯的底表面和电极是绝缘的，并且它们的顶部（和漏电极）通过可模制导电层连接。 在另一个实施例中，衬底的顶表面由绝缘帽覆盖，绝缘帽可以被翅片以改善热性能。 无源器件具有垂直于衬底表面的最长尺寸，并且位于翅片谷之间。 绝缘盖是适合于基板顶部的盖，其中模具锁定凹陷包含在盖周边内部边缘和基板配合边缘表面之间的连接处。