公开(公告)号：US20120216167A1

公开(公告)日：2012-08-23

申请号：US13504374

申请日：2010-10-27

Applicant: Chen-Feng Chang ,  Chin-Fang Shen ,  Hsien-Shih Chiu ,  I-Jye Lin ,  Tien-Chang Hsu ,  Yao-Wen Chang ,  Chun-Wei Lin ,  Po-Wei Lee

Inventor： Chen-Feng Chang ,  Chin-Fang Shen ,  Hsien-Shih Chiu ,  I-Jye Lin ,  Tien-Chang Hsu ,  Yao-Wen Chang ,  Chun-Wei Lin ,  Po-Wei Lee

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  H01L23/525 ,  H01L24/02 ,  H01L24/14 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311

Abstract: Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads.

Abstract translation: 这里公开了用于倒装芯片封装的粗化方法和装置。 倒装芯片包括几个外部焊盘和几个内部焊盘。 路由方法包括：基于外部焊盘的布置顺序设置外部序列; 基于内垫和外垫之间的连接关系设置几个内序列; 计算每个内部序列和外部序列的最长公共子序列，将内部焊盘和对应于最长公共子序列的外部焊盘之间的连接关系定义为直接连接，并且限定内部焊盘和外部焊盘之间的连接关系， 不符合迂回连线最长的共同后果; 基于内部焊盘和外部焊盘之间的连接关系建立倒装芯片的布线方案。

公开(公告)号：US20120126840A1

公开(公告)日：2012-05-24

申请号：US13240738

申请日：2011-09-22

Applicant: Dong-Hyuk Lee ,  Chi-Sung Oh

Inventor： Dong-Hyuk Lee ,  Chi-Sung Oh

IPC: G01R31/3187

CPC classification number: G11C29/48 ,  G11C29/1201 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/50 ,  H01L2224/0346 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/1146 ,  H01L2224/11622 ,  H01L2224/13005 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate; bumps disposed in a plurality of rows along a first axis direction of the semiconductor substrate; and test pads disposed in one or more columns along a second axis direction perpendicular to the first axis direction. The bumps and the test pads form a cross shape in the center portion of the semiconductor substrate. Disposing bumps in the central portion of the semiconductor substrate facilitates forming physical connections between stacked semiconductor devices of a semiconductor stack, regardless of the chip sizes.

Abstract translation: 半导体器件包括半导体衬底; 沿着半导体衬底的第一轴线方向设置成多行的凸块; 以及沿着垂直于第一轴线方向的第二轴线方向设置在一个或多个列中的测试焊盘。 凸块和测试焊盘在半导体衬底的中心部分形成十字形。 在半导体衬底的中心部分设置凸起有助于在半导体堆叠的堆叠半导体器件之间形成物理连接，而与芯片尺寸无关。

公开(公告)号：US20110100685A1

公开(公告)日：2011-05-05

申请号：US12985456

申请日：2011-01-06

Applicant: Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

Inventor： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

IPC: H05K1/09 ,  H05K3/00

CPC classification number: H01L21/563 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/14136 ,  H01L2224/26152 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/831 ,  H01L2224/83385 ,  H01L2225/06513 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/19041 ,  H01L2924/19043 ,  Y10S428/901 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/4921 ,  Y10T29/49222 ,  Y10T428/24273 ,  Y10T428/24322 ,  Y10T428/24331 ,  Y10T428/24339 ,  Y10T428/24347 ,  Y10T428/24479 ,  Y10T428/24529 ,  Y10T428/24545 ,  Y10T428/24612 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An electrical structure and method of forming. The electrical structure includes a first substrate, a first dielectric layer, an underfill layer, a first solder structure, and a second substrate. The first dielectric layer is formed over a top surface of the first substrate. The first dielectric layer includes a first opening extending through a top surface and a bottom surface of said first dielectric layer. The first solder structure is formed within the first opening and over a portion of the top surface of said first dielectric layer. The second substrate is formed over and in contact with the underfill layer.

Abstract translation: 一种电气结构和成型方法。 电结构包括第一衬底，第一介电层，底部填充层，第一焊料结构和第二衬底。 第一介电层形成在第一基板的顶表面上。 第一电介质层包括延伸穿过所述第一电介质层的顶表面和底表面的第一开口。 第一焊料结构形成在第一开口内以及在所述第一介电层的顶表面的一部分之上。 第二衬底形成在底部填充层上并与底部填充层接触。

公开(公告)号：US07615865B2

公开(公告)日：2009-11-10

申请号：US11751440

申请日：2007-05-21

Applicant: TaeWoo Kang ,  YoRim Lee ,  TaeKeun Lee

Inventor： TaeWoo Kang ,  YoRim Lee ,  TaeKeun Lee

IPC: H01L23/48

CPC classification number: H05K3/303 ,  H01L24/11 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/06515 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/14505 ,  H01L2224/14515 ,  H01L2224/16 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/0305 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00

Abstract: A system to support a die includes a substrate. A solder resist is disposed over the substrate. A first solder bump is disposed in the solder resist to provide electrical connectivity through the solder resist to the substrate. A second solder bump is formed over the solder resist to correspond with a peripheral edge or a corner of the die. The second solder bump provides standoff height physical support to the die.

Abstract translation: 支撑模具的系统包括基板。 在衬底上设置阻焊剂。 第一焊料凸点设置在阻焊剂中以提供通过阻焊剂到衬底的电连接。 在阻焊剂上形成第二焊料凸块，以对应于模具的周边边缘或拐角。 第二个焊料凸块提供了对模具的支座高度物理支撑。

公开(公告)号：US20080293232A1

公开(公告)日：2008-11-27

申请号：US11751440

申请日：2007-05-21

Applicant: TaeWoo KANG ,  YoRim LEE ,  TaeKeun LEE

Inventor： TaeWoo KANG ,  YoRim LEE ,  TaeKeun LEE

IPC: H01L21/60 ,  H01L23/48

CPC classification number: H05K3/303 ,  H01L24/11 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/06515 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/14505 ,  H01L2224/14515 ,  H01L2224/16 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/0305 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00

Abstract: A system to support a die includes a substrate. A solder resist is disposed over the substrate. A first solder bump is disposed in the solder resist to provide electrical connectivity through the solder resist to the substrate. A second solder bump is formed over the solder resist to correspond with a peripheral edge or a corner of the die. The second solder bump provides standoff height physical support to the die.

Abstract translation: 支撑模具的系统包括基板。 在衬底上设置阻焊剂。 第一焊料凸点设置在阻焊剂中以提供通过阻焊剂到衬底的电连接。 在阻焊剂上形成第二焊料凸块，以对应于模具的周边边缘或拐角。 第二个焊料凸块提供了对模具的支座高度物理支撑。

公开(公告)号：US06921018B2

公开(公告)日：2005-07-26

申请号：US10727856

申请日：2003-12-04

Applicant: Thomas George Ference ,  Wayne John Howell

Inventor： Thomas George Ference ,  Wayne John Howell

IPC: H01L21/60 ,  H01L23/485 ,  H01L25/065 ,  B23K31/02 ,  B23K35/12 ,  H01L21/44

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/0508 ,  H01L2224/05568 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14505 ,  H01L2224/17051 ,  H01L2224/17515 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2224/05155

Abstract: A multi-chip stack structure and method of fabrication are provided utilizing self-aligning electrical contact arrays. Two or more arrays of interconnection contacts are provided, with one array being a rough aligned contact array, and a second array being a high bandwidth contact array. The rough aligned contact array has larger contacts and at least a portion thereof which melts at a substantially lower temperature than the melting temperature of the contacts of the high bandwidth contact array. By positioning two integrated circuit chips in opposing relation with the arrays mechanically aligned therebetween, and applying heat to melt the contacts of the rough aligned array, the two chips will rotate to align the respective contacts of the high bandwidth contact arrays, thereby achieving improved connection reliability between the structures.

公开(公告)号：US20050104222A1

公开(公告)日：2005-05-19

申请号：US10944613

申请日：2004-09-20

Applicant: Se-Young Jeong ,  Gu-Sung Kim ,  Nam-Seog Kim ,  Gi-Hwan Park ,  Se-Yong Oh ,  Soon-Bum Kim ,  In-Young Lee

Inventor： Se-Young Jeong ,  Gu-Sung Kim ,  Nam-Seog Kim ,  Gi-Hwan Park ,  Se-Yong Oh ,  Soon-Bum Kim ,  In-Young Lee

IPC: H01L23/28 ,  H01L21/60 ,  H01L23/16 ,  H01L23/31 ,  H01L23/485 ,  H01L23/498 ,  H05K3/34 ,  H01L23/48

CPC classification number: H01L24/13 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06102 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/14155 ,  H01L2224/16 ,  H01L2224/1601 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29076 ,  H01L2224/30155 ,  H01L2224/30156 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/094 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01083 ,  H01L2224/13099 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/013

Abstract: A flip chip device may have a semiconductor chip with an active surface on which chip pads and a protective layer may be provided. Solder bumps may be provided on the active surface and electrically connected to the chip pads. And a solder bar may be provided on a portion of the protective layer. The solder bar may disperse thermal stress produced in the solder bumps. A metal core may be embedded within the solder bar. The flip chip device may be mounted on and flip-chip bonded to a substrate. The substrate may have land pads to which the solder bumps and the solder bar may be mechanically joined. The solder bar increases a joint area between the flip chip device and the substrate and reinforces solder connections therebetween.

Abstract translation: 倒装芯片器件可以具有其上可以设置有芯片焊盘和保护层的有源表面的半导体芯片。 可以在活性表面上提供焊料凸块并电连接到芯片焊盘。 并且可以在保护层的一部分上设置焊料条。 焊料棒可能会分散焊料凸点产生的热应力。 金属芯可以嵌入在焊条内。 倒装芯片器件可以安装在衬底上并倒装芯片结合到衬底上。 衬底可以具有焊盘，焊盘和焊条可以焊接到其上。 焊条增加了倒装芯片器件和衬底之间的接合面积，并加强了它们之间的焊接连接。

公开(公告)号：US20040108364A1

公开(公告)日：2004-06-10

申请号：US10727856

申请日：2003-12-04

Applicant: International Business Machines Corporation

Inventor： Thomas George Ference ,  Wayne John Howell

IPC: B23K031/00

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/0508 ,  H01L2224/05568 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14505 ,  H01L2224/17051 ,  H01L2224/17515 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2224/05155

Abstract: A multi-chip stack structure and method of fabrication are provided utilizing self-aligning electrical contact arrays. Two or more arrays of interconnection contacts are provided, with one array being a rough aligned contact array, and a second array being a high bandwidth contact array. The rough aligned contact array has larger contacts and at least a portion thereof which melts at a substantially lower temperature than the melting temperature of the contacts of the high bandwidth contact array. By positioning two integrated circuit chips in opposing relation with the arrays mechanically aligned therebetween, and applying heat to melt the contacts of the rough aligned array, the two chips will rotate to align the respective contacts of the high bandwidth contact arrays, thereby achieving improved connection reliability between the structures.

Abstract translation: 利用自对准电接触阵列提供多芯片堆叠结构和制造方法。 提供两个或更多个互连触点阵列，其中一个阵列是粗略对齐的触点阵列，第二阵列是高带宽触点阵列。 粗略对准的接触阵列具有较大的触点，并且其至少一部分在比高带宽接触阵列的触头的熔化温度低得多的温度下熔化。 通过将两个集成电路芯片定位成与其间机械对准的阵列相对的关系，并且施加热量以熔化粗略对准的阵列的触点，两个芯片将旋转以对齐高带宽接触阵列的各个触点，由此实现改进的连接 结构之间的可靠性。

公开(公告)号：US20020190390A1

公开(公告)日：2002-12-19

申请号：US10061247

申请日：2002-02-04

Applicant: Via Technologies, Inc.

Inventor： Hsueh-Chung Shelton Lu ,  Kenny Chang ,  Jimmy Huang

IPC: H01L023/48

CPC classification number: H01L24/14 ,  H01L23/50 ,  H01L23/64 ,  H01L24/02 ,  H01L2224/0235 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/14155 ,  H01L2224/14177 ,  H01L2224/45144 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/0106 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/48

Abstract: A bump arrangement of a flip-chip is disclosed. The bump arrangement comprises: a conductive bumps array formed at a core region of the flip-chip, a first ring of conductive bumps surrounding the conductive bumps array, a second ring surrounding the first ring, a third ring surrounding the second ring, and a fourth ring surrounding the third ring. In the four rings of bumps, the bumps of the third ring and the fourth ring are staggered each other and most of them are provided for I/O signal terminal so as to reduce the length conductive traces for I/O signal connection. The bumps in the first and the second ring are provided for power connection or ground connection. The first ring, the second ring, the third ring, the fourth ring and the bump at the core region are connected to conductive traces of an interconnection layer through a redistribution layer. The redistribution layer is located in between a passivation layer and the interconnection layer.

Abstract translation: 公开了倒装芯片的凸块布置。 所述凸块布置包括：形成在所述倒装芯片的芯区域处的导电凸块阵列，围绕所述导电凸块阵列的第一环导电凸块，围绕所述第一环的第二环，围绕所述第二环的第三环，以及 围绕第三环的第四环。 在四个凸起环中，第三环和第四环的凸起彼此交错，其大部分设置为I / O信号端子，以减少用于I / O信号连接的长度导电迹线。 第一和第二环中的凸块被提供用于电源连接或接地连接。 核心区域的第一环，第二环，第三环，第四环和凸起通过再分配层连接到互连层的导电迹线。 再分配层位于钝化层和互连层之间。

公开(公告)号：US20240321797A1

公开(公告)日：2024-09-26

申请号：US18455573

申请日：2023-08-24

Applicant: Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

Inventor： Yoshiaki SHIMOOKA

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/11472 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/14136 ,  H01L2224/14146

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate and an array portion. The array portion includes a plurality of metal portions arranged on the semiconductor substrate. When a virtual quadrilateral circumscribing minimally a contour shape of the array portion on the semiconductor substrate is set, the contour shape of the array portion does not overlap each of four vertices of the virtual quadrilateral.