公开(公告)号：US20210280523A1

公开(公告)日：2021-09-09

申请号：US16916339

申请日：2020-06-30

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Aniket Patil ,  Marcus Hsu ,  David Fraser Rae

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: Integrated circuit (IC) packages employing split, double-sided IC metallization structures to facilitate a semiconductor die (“IC die”) module employing stacked dice, and related fabrication methods are disclosed. Multiple IC dice in the IC package are stacked and bonded together in a back-to-back, top and bottom IC die configuration in an IC die module, which can minimize the overall height of the IC package. The metallization structure is split between separate top and bottom metallization structures adjacent to respective top and bottom surfaces of the IC die module to facilitate die-to-die and external electrical connections to the dice. The top and bottom metallization structures can be double-sided by exposing substrate interconnects on respective inner and outer surfaces for respective die and external electrical interconnections. In other exemplary aspects, the top and bottom metallization structures can include redistribution layers (RDLs) to provide increased electrical conductivity between die interconnects and substrate interconnects.

公开(公告)号：US10516092B2

公开(公告)日：2019-12-24

申请号：US15256501

申请日：2016-09-02

Applicant: QUALCOMM Incorporated

Inventor： Jon Gregory Aday ,  Hong Bok We ,  Steve Joseph Bezuk ,  Nicholas Ian Buchan

IPC: H01L27/20 ,  H01L41/113 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/78 ,  H01L21/56 ,  H01L21/768 ,  H01L41/053

Abstract: A package may include a substrate and a semiconductor die with the substrate having a smaller width than the semiconductor die and encapsulated in a mold compound. In one example, the package may be a wafer level package that allows an external connection on the backside of the package to enable manufacturing in a panel or wafer form.

公开(公告)号：US10157823B2

公开(公告)日：2018-12-18

申请号：US14693820

申请日：2015-04-22

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook Kim ,  Hong Bok We ,  Jae Sik Lee ,  Shiqun Gu

IPC: H01L23/48 ,  H01L29/40 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683

Abstract: A high density fan out package structure may include a contact layer. The contact layer includes a conductive interconnect layer having a first surface facing an active die and a second surface facing a redistribution layer. The high density fan out package structure has a barrier layer on the first surface of the conductive interconnect layer. The high density fan out package structure may also include the redistribution layer, which has conductive routing layers. The conductive routing layers may be configured to couple a first conductive interconnect to the conductive interconnect layer. The high density fan out package structure may further include a first via coupled to the barrier liner and configured to couple with a second conductive interconnect to the active die.

公开(公告)号：US09679855B1

公开(公告)日：2017-06-13

申请号：US15082954

申请日：2016-03-28

Applicant: QUALCOMM Incorporated

Inventor： Jae Sik Lee ,  Hong Bok We ,  Dong Wook Kim ,  Jon Aday

IPC: H01L23/544 ,  H01L21/301 ,  H01L21/46 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L22/34 ,  H01L23/3178 ,  H01L23/544 ,  H01L2223/5446 ,  H01L2224/11

Abstract: Some implementations provide a semiconductor device (e.g., die, wafer) that includes a substrate, that is configured with trenches that are dry-etched into a surface of the substrate inside an area defined by scribe lines of the substrate. A crack stop structure is provided for the semiconductor device that includes a polymer dielectric layer coating that fills the trenches with a polymer dielectric material and provides a dielectric layer over the surface of the substrate inside the area. The polymer dielectric layer coating and trenches are configured to reduce cracking or chipping of the substrate in the area defined by scribe lines after cutting.

公开(公告)号：US09659850B2

公开(公告)日：2017-05-23

申请号：US14563854

申请日：2014-12-08

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Kyu-Pyung Hwang ,  Young Kyu Song ,  Dong Wook Kim

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/16 ,  H01L23/66 ,  H01L23/482 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/4824 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/66 ,  H01L24/83 ,  H01L2223/6622 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/162 ,  H01L2924/00

Abstract: A package substrate that includes a first portion and a redistribution portion. The first portion is configured to operate as a capacitor. The first portion includes a first dielectric layer, a first set of metal layers in the dielectric layer, a first via in the dielectric layer, a second set of metal layers in the dielectric layer, and a second via in the dielectric layer. The first via is coupled to the first set of metal layers. The first via and the first set of metal layers are configured to provide a first electrical path for a ground signal. The second via is coupled to the second set of metal layers. The second via and the second set of metal layers are configured to provide a second electrical path for a power signal. The redistribution portion includes a second dielectric layer, and a set of interconnects.

公开(公告)号：US09628052B2

公开(公告)日：2017-04-18

申请号：US14249189

申请日：2014-04-09

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Dong Wook Kim ,  Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H01L23/50 ,  H03K3/013 ,  H05K1/18 ,  H05K1/03 ,  H05K3/46 ,  G05F3/08 ,  H05K3/30 ,  H01L23/498 ,  H01L23/00

CPC classification number: H03K3/013 ,  G05F3/08 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/13091 ,  H01L2924/15311 ,  H05K1/0306 ,  H05K1/183 ,  H05K1/184 ,  H05K3/306 ,  H05K3/4697 ,  H05K2201/10015 ,  Y10T29/49139 ,  H01L2924/00

Abstract: An embedded multi-terminal capacitor embedded in a substrate cavity includes at least one metal layer patterned into a plurality of power rails and a plurality of ground rails. The substrate includes an external power network.

公开(公告)号：US09596768B2

公开(公告)日：2017-03-14

申请号：US14196481

申请日：2014-03-04

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Dong Wook Kim ,  Jae Sik Lee ,  Shiqun Gu

IPC: H05K3/42 ,  H05K1/03 ,  H05K1/11 ,  H05K3/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K3/426 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L2224/18 ,  H05K1/0306 ,  H05K1/0313 ,  H05K1/111 ,  H05K1/115 ,  H05K3/0094

Abstract: A substrate includes a plurality of vias that are lined with dielectric polymer having a substantially uniform thickness. This substantial uniform thickness provides a lumen within each dielectric-polymer-layer-lined via that is substantially centered within the via. Subsequent deposition of metal into the lumen for each dielectric-polymer-layer-lined via thus provides conductive vias having substantially centered metal conductors.

Abstract translation: 衬底包括多个具有基本上均匀厚度的介电聚合物的通孔。 这个基本上均匀的厚度提供了在每个介质聚合物层衬里的通孔内的管腔，其基本上位于通孔内。 因此，随后将金属沉积到每个介质聚合物层衬里的通孔的内腔中，由此提供具有基本中心的金属导体的导电通孔。

公开(公告)号：US09490226B2

公开(公告)日：2016-11-08

申请号：US14462265

申请日：2014-08-18

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Hong Bok We ,  Dong Wook Kim ,  Kyu-Pyung Hwang

IPC: H01L23/52 ,  H01L23/00 ,  H01L23/34 ,  H01L23/373 ,  H01L23/498 ,  H01L21/48 ,  H05K1/02

CPC classification number: H01L24/17 ,  H01L21/4857 ,  H01L23/34 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/10175 ,  H01L2224/131 ,  H01L2224/16111 ,  H01L2224/16112 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/17519 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83104 ,  H05K1/0207 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Provided herein is an integrated device that includes a substrate, a die, a heat-dissipation layer located between the substrate and the die, and a first interconnect configured to couple the die to the heat-dissipation layer. The heat-dissipation layer may be configured to provide an electrical path for a ground signal. The first interconnect may be further configured to conduct heat from the die to the heat-dissipation layer. The integrated device may also include a second interconnect configured to couple the die to the substrate. The second interconnect may be further configured to conduct a power signal between the die and the substrate. The integrated device may also include a dielectric layer located between the heat-dissipation layer and the substrate, and a solder-resist layer located between the die and the heat-dissipation layer.

Abstract translation: 本文提供了一种集成器件，其包括衬底，管芯，位于衬底和管芯之间的散热层和被配置为将管芯耦合到散热层的第一互连。 散热层可以被配置成为接地信号提供电路径。 第一互连可以被进一步配置成将热量从管芯传导到散热层。 集成器件还可以包括配置成将管芯耦合到衬底的第二互连。 第二互连可以被进一步配置为在管芯和衬底之间传导功率信号。 集成器件还可以包括位于散热层和衬底之间的介电层，以及位于管芯和散热层之间的阻焊层。

公开(公告)号：US09368450B1

公开(公告)日：2016-06-14

申请号：US14832363

申请日：2015-08-21

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Hong Bok We ,  Jae Sik Lee ,  Dong Wook Kim

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538

CPC classification number: H01L23/5385 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An integrated device package includes a first die, a second die, an encapsulation portion coupled to the first die and the second die, and a redistribution portion coupled to the encapsulation portion. The encapsulation portion includes an encapsulation layer, a bridge, and a first via. The bridge is at least partially embedded in the encapsulation layer. The bridge is configured to provide a first electrical path for a first signal between the first die and the second die. The first via is in the encapsulation layer. The first via is coupled to the bridge. The first via and the bridge are configured to provide a second electrical path for a second signal to the first die. The redistribution portion includes at least one dielectric layer, and at least one interconnect, in the dielectric layer, coupled to the first via.

Abstract translation: 集成器件封装包括第一管芯，第二管芯，耦合到第一管芯和第二管芯的封装部分，以及耦合到封装部分的再分配部分。 封装部分包括封装层，桥和第一通孔。 该桥至少部分地嵌入在封装层中。 桥被配置成为第一管芯和第二管芯之间的第一信号提供第一电路径。 第一个通道在封装层中。 第一个通道耦合到桥。 第一通孔和桥被配置为为第一模具提供第二信号的第二电路径。 再分配部分包括耦合到第一通孔的介电层中的至少一个电介质层和至少一个互连。

公开(公告)号：US20160013125A1

公开(公告)日：2016-01-14

申请号：US14329646

申请日：2014-07-11

Applicant: QUALCOMM INCORPORATED

Inventor： Dong Wook Kim ,  Young Kyu Song ,  Kyu-Pyung Hwang ,  Hong Bok We

IPC: H01L23/498 ,  H05K3/28 ,  H05K3/46 ,  H01L21/48 ,  H05K1/02

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/19107 ,  H05K1/0298 ,  H05K3/284 ,  H05K3/46 ,  H05K2203/1316

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first interconnect coupled to the substrate, and a second interconnect surrounding the first interconnect. The second interconnect may be configured to provide an electrical connection to ground. In some implementations, the second interconnect includes a plate. In some implementations, the integrated device also includes a dielectric material between the first interconnect and the second interconnect. In some implementations, the integrated device also includes a mold surrounding the second interconnect. In some implementations, the first interconnect is configured to conduct a power signal in a first direction. In some implementations, the second interconnect is configured to conduct a grounding signal in a second direction. In some implementations, the second direction is different from the first direction. In some implementations, the integrated device may be a package-on-package (PoP) device.

Abstract translation: 一些新颖的特征涉及包括衬底，耦合到衬底的第一互连和围绕第一互连的第二互连的集成器件。 第二互连可以被配置为提供到地的电连接。 在一些实现中，第二互连包括板。 在一些实施方案中，集成器件还包括在第一互连和第二互连之间的介电材料。 在一些实施方案中，集成装置还包括围绕第二互连的模具。 在一些实现中，第一互连被配置为在第一方向上传导功率信号。 在一些实现中，第二互连被配置为在第二方向上传导接地信号。 在一些实施方式中，第二方向与第一方向不同。 在一些实施方式中，集成器件可以是封装封装（PoP）器件。