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    Embedded package substrate capacitor
    1.
    发明授权
    Embedded package substrate capacitor 有权
    嵌入式封装衬底电容器

    公开(公告)号：US09502490B2

    公开(公告)日：2016-11-22

    申请号：US14283980

    申请日：2014-05-21

    Applicant: QUALCOMM Incorporated

    Inventor： Hong Bok We ,  Kyu-Pyung Hwang ,  Young Kyu Song ,  Dong Wook Kim

    IPC: H01L49/02 ,  H01L23/498 ,  H05K1/18 ,  H05K3/46 ,  H01L23/50

    CPC classification number: H01L28/40 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K1/185 ,  H05K3/4602 ,  H01L2924/014

    Abstract: A package substrate is provided that includes a core substrate and a capacitor embedded in the core substrate including a first side. The capacitor includes a first electrode and a second electrode disposed at opposite ends of the capacitor. The package also includes a first power supply metal plate extending laterally in the core substrate. The first power supply metal plate is disposed directly on the first electrode of the capacitor from the first side of the core substrate. A first via extending perpendicular to the first metal plate and connected to the first power supply metal plate from the first side of the core substrate.

    Abstract translation: 提供一种封装基板，其包括芯基板和嵌入在包括第一侧的芯基板中的电容器。 电容器包括设置在电容器的相对端的第一电极和第二电极。 封装还包括在芯基板中横向延伸的第一电源金属板。 第一电源金属板从芯基板的第一侧直接设置在电容器的第一电极上。 第一通孔，其垂直于第一金属板延伸并从芯基板的第一侧连接到第一电源金属板。

    INTEGRATED DEVICE PACKAGE COMPRISING SILICON BRIDGE IN PHOTO IMAGEABLE LAYER
    3.
    发明申请
    INTEGRATED DEVICE PACKAGE COMPRISING SILICON BRIDGE IN PHOTO IMAGEABLE LAYER 审中-公开
    在照相图像层中包含硅桥的集成设备包

    公开(公告)号：US20160141234A1

    公开(公告)日：2016-05-19

    申请号：US14543560

    申请日：2014-11-17

    Applicant: QUALCOMM Incorporated

    Inventor： Hong Bok We ,  Dong Wook Kim ,  Jae Sik Lee ,  Kyu-Pyung Hwang ,  Young Kyu Song

    IPC: H01L23/498

    CPC classification number: H01L23/5385 ,  H01L23/49827 ,  H01L23/5384 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K3/3436 ,  H05K3/4694 ,  H05K2203/061 ,  H01L2924/00

    Abstract: An integrated device package includes a base portion, a redistribution portion, a first die and a second die. The base portion includes a photo imageable layer, a bridge that is at least partially embedded in the photo imageable layer, and a set of vias in the photo imageable layer. The bridge includes a first set of interconnects comprising a first density. The set of vias includes a second density. The redistribution portion is coupled to base portion. The redistribution portion includes at least one dielectric layer, a second set of interconnects coupled to the first set of interconnects, and a third set of interconnects coupled to the set of vias. The first die is coupled to the redistribution portion. The second die is coupled to the redistribution portion, where the first die and the second die are coupled to each other through an electrical path that includes the bridge.

    Abstract translation: 集成器件封装包括基部，再分配部分，第一管芯和第二管芯。 基部包括可照像图像层，至少部分地嵌入在可照光成像层中的桥以及可照片成像层中的一组通孔。 桥包括包括第一密度的第一组互连。 该组通孔包括第二密度。 再分配部分耦合到基部。 再分配部分包括耦合到第一组互连的至少一个电介质层，第二组互连以及耦合到该组通孔的第三组互连。 第一管芯耦合到再分配部分。 第二管芯耦合到再分配部分，其中第一管芯和第二管芯通过包括桥的电路相互连接。

    INTEGRATED DEVICE COMPRISING VIA WITH SIDE BARRIER LAYER TRAVERSING ENCAPSULATION LAYER
    4.
    发明申请
    INTEGRATED DEVICE COMPRISING VIA WITH SIDE BARRIER LAYER TRAVERSING ENCAPSULATION LAYER 有权
    整合装置通过与阻挡层隔离的包围层

    公开(公告)号：US20150228556A1

    公开(公告)日：2015-08-13

    申请号：US14274517

    申请日：2014-05-09

    Applicant: QUALCOMM Incorporated

    Inventor： Jae Sik Lee ,  Hong Bok We ,  Dong Wook Kim ,  Shiqun Gu

    IPC: H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/50

    CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/49827 ,  H01L23/50 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1533

    Abstract: Some novel features pertain to an integrated device that includes an encapsulation layer, a via structure traversing the encapsulation layer, and a pad. The via structure includes a via that includes a first side, a second side, and a third side. The via structure also includes a barrier layer surrounding at least the first side and the third side of the via. The pad is directly coupled to the barrier layer of the via structure. In some implementations, the integrated device includes a first dielectric layer coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a substrate coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a first die coupled to the substrate, where the encapsulation layer encapsulates the first die. In some implementations, the via includes a portion configured to operate as a pad.

    Abstract translation: 一些新颖的特征涉及包括封装层，穿过封装层的通孔结构和焊盘的集成器件。 通孔结构包括通孔，其包括第一侧，第二侧和第三侧。 通孔结构还包括至少围绕通孔的第一侧和第三侧的阻挡层。 焊盘直接耦合到通孔结构的阻挡层。 在一些实施方案中，集成器件包括耦合到封装层的第一表面的第一介电层。 在一些实施方案中，集成器件包括耦合到封装层的第一表面的衬底。 在一些实施方案中，集成器件包括耦合到衬底的第一管芯，其中封装层封装第一管芯。 在一些实施方式中，通孔包括被配置为作为垫进行操作的部分。

    SMALL FORM FACTOR MAGNETIC SHIELD FOR MAGNETORESTRICTIVE RANDOM ACCESS MEMORY (MRAM)
    5.
    发明申请
    SMALL FORM FACTOR MAGNETIC SHIELD FOR MAGNETORESTRICTIVE RANDOM ACCESS MEMORY (MRAM) 有权
    用于磁阻随机存取存储器（MRAM）的小型磁阻电磁屏蔽

    公开(公告)号：US20150048465A1

    公开(公告)日：2015-02-19

    申请号：US14499027

    申请日：2014-09-26

    Applicant: QUALCOMM Incorporated

    Inventor： Shiqun Gu ,  Rongtian Zhang ,  Vidhya Ramachandran ,  Dong Wook Kim

    IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

    CPC classification number: H01L43/12 ,  H01L23/3121 ,  H01L23/552 ,  H01L23/645 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2924/0002 ,  H01L2924/1435 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

    Abstract: Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.

    Abstract translation: 一些实施方案提供了包括包括几个MRAM单元的磁阻随机存取存储器（MRAM）单元阵列的管芯。 芯片还包括位于MRAM单元阵列上方的第一铁磁层，位于MRAM单元阵列下方的第二铁磁层和位于至少一个MRAM单元周围的几个通孔。 通孔包括铁磁材料。 在一些实施方案中，第一铁磁层，第二铁磁层和几个通孔限定用于MRAM单元阵列的磁屏蔽。 MRAM单元可以包括磁性隧道结（MTJ）。 在一些实施方案中，几个通孔至少穿过管芯的金属层和电介质层。 在一些实施方案中，通孔通过衬底通孔。 在一些实施方案中，铁磁材料具有高磁导率和高B饱和度。

    Small form factor magnetic shield for magnetorestrictive random access memory (MRAM)
    6.
    发明授权
    Small form factor magnetic shield for magnetorestrictive random access memory (MRAM) 有权

    公开(公告)号：US08884408B2

    公开(公告)日：2014-11-11

    申请号：US13777475

    申请日：2013-02-26

    Applicant: QUALCOMM Incorporated

    Inventor： Shiqun Gu ,  Rongtian Zhang ,  Vidhya Ramachandran ,  Dong Wook Kim

    IPC: H01L23/552 ,  H01L43/02

    Abstract: Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.

    BANDPASS FILTER IMPLEMENTATION ON A SINGLE LAYER USING SPIRAL CAPACITORS
    7.
    发明申请
    BANDPASS FILTER IMPLEMENTATION ON A SINGLE LAYER USING SPIRAL CAPACITORS 有权
    使用螺旋电容器的单层滤波器实现

    公开(公告)号：US20140266508A1

    公开(公告)日：2014-09-18

    申请号：US13835211

    申请日：2013-03-15

    Applicant: QUALCOMM INCORPORATED

    Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Changhan Hobie Yun ,  Dong Wook Kim

    IPC: H03H7/01 ,  H03H3/00 ,  H01G4/40

    CPC classification number: H03H7/0115 ,  H01G4/40 ,  H03H3/00 ,  H03H7/12 ,  H05K1/162 ,  H05K2201/09236 ,  Y10T29/43 ,  Y10T29/49016

    Abstract: A planar capacitor includes, in part, a first metal line forming spiral-shaped loops around one of its end point, and a second metal line forming spiral-shaped loops between the loops of the first metal line. The first and second metal lines are coplanar, formed on an insulating layer, and form the first and second plates of the planar capacitor. The planar capacitor may be used to form a filter. Such a filter includes a first metal line forming first spiral-shaped loops, a second metal line forming second spiral-shaped loops, and a third metal line—coplanar with the first and second metal lines—forming loops between the loops of the first and second metal lines. The filter further includes a first inductor coupled between the first and third metal lines, and a second inductor coupled between the second and third metal lines.

    Abstract translation: 平面电容器部分地包括围绕其端点之一形成螺旋形环的第一金属线和在第一金属线的环之间形成螺旋形环的第二金属线。 第一和第二金属线是共面的，形成在绝缘层上，并形成平面电容器的第一和第二板。 平面电容器可以用于形成滤波器。 这种过滤器包括形成第一螺旋形环的第一金属线，形成第二螺旋状环的第二金属线和与第一和第二金属线形成环之间的第一和第二金属线形成环的第三金属线 - 共面， 第二条金属线。 滤波器还包括耦合在第一和第三金属线之间的第一电感器和耦合在第二和第三金属线之间的第二电感器。

    High density fan out package structure
    8.
    发明授权
    High density fan out package structure 有权

    公开(公告)号：US10157823B2

    公开(公告)日：2018-12-18

    申请号：US14693820

    申请日：2015-04-22

    Applicant: QUALCOMM Incorporated

    Inventor： Dong Wook Kim ,  Hong Bok We ,  Jae Sik Lee ,  Shiqun Gu

    IPC: H01L23/48 ,  H01L29/40 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683

    Abstract: A high density fan out package structure may include a contact layer. The contact layer includes a conductive interconnect layer having a first surface facing an active die and a second surface facing a redistribution layer. The high density fan out package structure has a barrier layer on the first surface of the conductive interconnect layer. The high density fan out package structure may also include the redistribution layer, which has conductive routing layers. The conductive routing layers may be configured to couple a first conductive interconnect to the conductive interconnect layer. The high density fan out package structure may further include a first via coupled to the barrier liner and configured to couple with a second conductive interconnect to the active die.

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