公开(公告)号：US20150325496A1

公开(公告)日：2015-11-12

申请号：US14272494

申请日：2014-05-07

Applicant: QUALCOMM Incorporated

Inventor： Reynante Tamunan Alvarado ,  Lizabeth Ann Keser ,  Steve Joseph Bezuk

IPC: H01L23/48 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/4896 ,  H01L21/56 ,  H01L21/76897 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13101 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/78301 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15738 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/01014 ,  H01L2924/00012

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first die coupled to the substrate, a first encapsulation layer coupled to the substrate and the first die, and a second encapsulation layer in the first encapsulation layer. The second encapsulation layer includes a set of wires configured to operate as vias. In some implementations, the integrated device includes a set of vias in the first encapsulation layer. In some implementations, the integrated device further includes a second die coupled to the substrate. In some implementations, the second encapsulation layer is positioned between the first die and the second die. In some implementations, the integrated device further includes a cavity in the first encapsulation layer, where the second encapsulation layer is positioned in the cavity. In some implementations, the cavity has a wall that is non-vertical. In some implementations, at least one of the wires is non-vertical.

Abstract translation: 一些新颖的特征涉及一种集成器件，其包括衬底，耦合到衬底的第一管芯，耦合到衬底和第一管芯的第一封装层，以及第一封装层中的第二封装层。 第二封装层包括一组配置为作为过孔工作的导线。 在一些实现中，集成器件包括第一封装层中的一组通孔。 在一些实施方案中，集成器件还包括耦合到衬底的第二管芯。 在一些实施方案中，第二封装层位于第一管芯和第二管芯之间。 在一些实施方案中，集成器件还包括第一封装层中的空腔，其中第二封装层位于空腔中。 在一些实施方案中，空腔具有非垂直的壁。 在一些实施方案中，至少一条导线是非垂直的。

公开(公告)号：US10516092B2

公开(公告)日：2019-12-24

申请号：US15256501

申请日：2016-09-02

Applicant: QUALCOMM Incorporated

Inventor： Jon Gregory Aday ,  Hong Bok We ,  Steve Joseph Bezuk ,  Nicholas Ian Buchan

IPC: H01L27/20 ,  H01L41/113 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/78 ,  H01L21/56 ,  H01L21/768 ,  H01L41/053

Abstract: A package may include a substrate and a semiconductor die with the substrate having a smaller width than the semiconductor die and encapsulated in a mold compound. In one example, the package may be a wafer level package that allows an external connection on the backside of the package to enable manufacturing in a panel or wafer form.

公开(公告)号：US09318405B2

公开(公告)日：2016-04-19

申请号：US14702276

申请日：2015-05-01

Applicant: QUALCOMM Incorporated

Inventor： Jianwen Xu ,  Lizabeth Ann Keser ,  William Stone ,  Steve Joseph Bezuk ,  Nicholas Ka Ming Yu

IPC: H01L23/12 ,  H01L21/00 ,  H01L23/31 ,  H01L23/528 ,  H01L23/532 ,  H01L23/498 ,  H01L21/78 ,  H01L23/28 ,  H01L21/56

CPC classification number: H01L23/3114 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/525 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/5329 ,  H01L29/0657 ,  H01L2224/11

Abstract: A wafer level package device may include a molding compound that encapsulates a substrate, a back end of line and front end of line layer on the substrate and a passivation layer of a redistribution layer without encapsulating a metal layer on the passivation layer. The molding compound may eliminate sidewall chipping and cracking as well as reduce the need for back side lamination.

Abstract translation: 晶片级封装器件可以包括封装衬底，衬底的后端和衬底上的线层前端的模制化合物以及再分配层的钝化层，而不在钝化层上封装金属层。 模塑料可以消除侧壁碎裂和破裂，并且减少对背面层压的需要。

公开(公告)号：US09209110B2

公开(公告)日：2015-12-08

申请号：US14272494

申请日：2014-05-07

Applicant: QUALCOMM Incorporated

Inventor： Reynante Tamunan Alvarado ,  Lizabeth Ann Keser ,  Steve Joseph Bezuk

IPC: H01L23/04 ,  H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/481 ,  H01L21/4896 ,  H01L21/56 ,  H01L21/76897 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13101 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/78301 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15738 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/01014 ,  H01L2924/00012

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first die coupled to the substrate, a first encapsulation layer coupled to the substrate and the first die, and a second encapsulation layer in the first encapsulation layer. The second encapsulation layer includes a set of wires configured to operate as vias. In some implementations, the integrated device includes a set of vias in the first encapsulation layer. In some implementations, the integrated device further includes a second die coupled to the substrate. In some implementations, the second encapsulation layer is positioned between the first die and the second die. In some implementations, the integrated device further includes a cavity in the first encapsulation layer, where the second encapsulation layer is positioned in the cavity. In some implementations, the cavity has a wall that is non-vertical. In some implementations, at least one of the wires is non-vertical.

Abstract translation: 一些新颖的特征涉及一种集成器件，其包括衬底，耦合到衬底的第一管芯，耦合到衬底和第一管芯的第一封装层，以及第一封装层中的第二封装层。 第二封装层包括一组配置为作为过孔工作的导线。 在一些实现中，集成器件包括第一封装层中的一组通孔。 在一些实施方案中，集成器件还包括耦合到衬底的第二管芯。 在一些实施方案中，第二封装层位于第一管芯和第二管芯之间。 在一些实施方案中，集成器件还包括第一封装层中的空腔，其中第二封装层位于空腔中。 在一些实施方案中，空腔具有非垂直的壁。 在一些实施方案中，至少一条导线是非垂直的。

公开(公告)号：US09171782B2

公开(公告)日：2015-10-27

申请号：US13960110

申请日：2013-08-06

Applicant: QUALCOMM Incorporated

Inventor： Christine Sung-An Hau-Riege ,  You-Wen Yau ,  Kevin Patrick Caffey ,  Lizabeth Ann Keser ,  Gene Hyde McAllister ,  Reynante Tamunan Alvarado ,  Steve Joseph Bezuk ,  Damion Bryan Gastelum

IPC: H01L27/118 ,  H01L23/485 ,  H01L21/768 ,  H01L23/532 ,  H01L23/525

CPC classification number: H01L23/485 ,  H01L21/76841 ,  H01L21/76895 ,  H01L23/525 ,  H01L23/53238 ,  H01L23/53266 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/1134 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/01074 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014

Abstract: Some implementations provide a semiconductor device (e.g., die) that includes a substrate, several metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the plurality of metal layers, a first metal redistribution layer coupled to the pad, and a second metal redistribution layer coupled to the first metal redistribution layer. The second metal redistribution layer includes a cobalt tungsten phosphorous material. In some implementations, the first metal redistribution layer is a copper layer. In some implementations, the semiconductor device further includes a first underbump metallization (UBM) layer and a second underbump metallization (UBM) layer.

Abstract translation: 一些实施方案提供了一种半导体器件（例如，管芯），其包括衬底，耦合到衬底的几个金属层和电介质层，耦合到多个金属层中的一个的焊盘，耦合到衬垫的第一金属再分布层，以及 耦合到第一金属再分配层的第二金属再分配层。 第二金属再分布层包括钴钨磷材料。 在一些实施方案中，第一金属再分配层是铜层。 在一些实施方案中，半导体器件还包括第一底部浸渍金属化（UBM）层和第二底部金属化（UBM）层。