公开(公告)号：US09318405B2

公开(公告)日：2016-04-19

申请号：US14702276

申请日：2015-05-01

Applicant: QUALCOMM Incorporated

Inventor： Jianwen Xu ,  Lizabeth Ann Keser ,  William Stone ,  Steve Joseph Bezuk ,  Nicholas Ka Ming Yu

IPC: H01L23/12 ,  H01L21/00 ,  H01L23/31 ,  H01L23/528 ,  H01L23/532 ,  H01L23/498 ,  H01L21/78 ,  H01L23/28 ,  H01L21/56

CPC classification number: H01L23/3114 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/525 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/5329 ,  H01L29/0657 ,  H01L2224/11

Abstract: A wafer level package device may include a molding compound that encapsulates a substrate, a back end of line and front end of line layer on the substrate and a passivation layer of a redistribution layer without encapsulating a metal layer on the passivation layer. The molding compound may eliminate sidewall chipping and cracking as well as reduce the need for back side lamination.

Abstract translation: 晶片级封装器件可以包括封装衬底，衬底的后端和衬底上的线层前端的模制化合物以及再分配层的钝化层，而不在钝化层上封装金属层。 模塑料可以消除侧壁碎裂和破裂，并且减少对背面层压的需要。

公开(公告)号：US12218041B2

公开(公告)日：2025-02-04

申请号：US17237828

申请日：2021-04-22

Applicant: QUALCOMM Incorporated

Inventor： Jihong Choi ,  Giridhar Nallapati ,  William Stone ,  Jianwen Xu ,  Jonghae Kim ,  Periannan Chidambaram ,  Ahmer Syed

IPC: H01L23/498 ,  H01L21/48 ,  H01L49/02

Abstract: Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate and related fabrication methods. The embedded capacitor can be coupled to a power distribution network (PDN) to provide decoupling capacitance to reduce current-resistance (IR) drop. The RDL substrate is disposed between the IC chip(s) and the package substrate to minimize distance between the embedded capacitor(s) and the IC chip(s) to reduce the parasitic inductance in the PDN, thus reducing PDN noise. With the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections between the package substrate and the IC chip(s). In this regard, the RDL substrate includes an outer RDL layer adjacent to the IC chip(s) to support small pitch metal interconnects as well as provide fan-out capability. This provides enhanced connectivity compatibility with higher-density die interconnect IC chips while also supporting a closer located embedded capacitor in the PDN.

公开(公告)号：US11784157B2

公开(公告)日：2023-10-10

申请号：US17339830

申请日：2021-06-04

Applicant: QUALCOMM Incorporated

Inventor： Li-Sheng Weng ,  Charles David Paynter ,  Ryan Lane ,  Jianwen Xu ,  William Stone

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L24/73 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L24/20 ,  H01L24/24 ,  H01L25/105 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17163 ,  H01L2224/2105 ,  H01L2224/24145 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A package comprising a first integrated device comprising a plurality of first pillar interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a metallization portion located over the first integrated device and the encapsulation layer, wherein the metallization portion includes at least one passivation layer and a plurality of metallization layer interconnects, wherein the plurality of first pillar interconnects is coupled to the plurality of metallization layer interconnects; and a second integrated device comprising a plurality of second pillar interconnects, wherein the second integrated device is coupled to the plurality of metallization layer interconnects through a plurality of second pillar interconnects and a plurality of solder interconnects.

公开(公告)号：US20220344250A1

公开(公告)日：2022-10-27

申请号：US17237828

申请日：2021-04-22

Applicant: QUALCOMM Incorporated

Inventor： Jihong Choi ,  Giridhar Nallapati ,  William Stone ,  Jianwen Xu ,  Jonghae Kim ,  Periannan Chidambaram ,  Ahmer Syed

IPC: H01L23/498 ,  H01L49/02 ,  H01L21/48

Abstract: Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate and related fabrication methods. The embedded capacitor can be coupled to a power distribution network (PDN) to provide decoupling capacitance to reduce current-resistance (IR) drop. The RDL substrate is disposed between the IC chip(s) and the package substrate to minimize distance between the embedded capacitor(s) and the IC chip(s) to reduce the parasitic inductance in the PDN, thus reducing PDN noise. With the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections between the package substrate and the IC chip(s). In this regard, the RDL substrate includes an outer RDL layer adjacent to the IC chip(s) to support small pitch metal interconnects as well as provide fan-out capability. This provides enhanced connectivity compatibility with higher-density die interconnect IC chips while also supporting a closer located embedded capacitor in the PDN.

公开(公告)号：US10141202B2

公开(公告)日：2018-11-27

申请号：US13898427

申请日：2013-05-20

Applicant: QUALCOMM Incorporated

Inventor： Reynante Tamunan Alvarado ,  Lizabeth Ann Keser ,  Jianwen Xu

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/78 ,  H01L21/311 ,  B23K26/40 ,  B23K26/364 ,  B23K103/16 ,  B23K26/382

Abstract: Some implementations provide a semiconductor device that includes a substrate, several metal and dielectric layers coupled to the substrate, and a pad coupled to one of the several metal layers. The semiconductor device also includes a first metal layer coupled to the pad and an under bump metallization layer coupled to the first metal redistribution layer. The semiconductor device further includes a mold layer covering a first surface of the semiconductor device and at least a side portion of the semiconductor device. In some implementations, the mold layer is an epoxy layer. In some implementations, the first surface of the semiconductor device is the top side of the semiconductor device. In some implementations, the mold layer covers the at least side portion of the semiconductor device such that a side portion of at least one of the several metal layers and dielectric layers is covered with the mold layer.

公开(公告)号：US20130244384A1

公开(公告)日：2013-09-19

申请号：US13890625

申请日：2013-05-09

Applicant: QUALCOMM Incorporated

Inventor： Mark Wendell Schwarz ,  Jianwen Xu

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/11 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/49811 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3436 ,  Y02P70/613 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate having a first side and a second side, the second side having a mounting location for at least one semiconductor element, and the first side having a plurality of locations electrically connected to locations on the second side. A plurality of electrically conductive interconnects are provided at the locations, each having a first end attached at the location and a second end spaced from the substrate, and an encapsulant partially encapsulates the plurality of interconnects and has a surface lying in a first plane. The second ends are located on the side of the first plane opposite from the substrate first side, an annular space in the encapsulant surrounds each of the plurality of electrically conductive interconnects, and the annular space has a bottom located between the first plane and the substrate first side. Also a method for making such a semiconductor device.

Abstract translation: 半导体器件包括具有第一侧和第二侧的衬底，第二侧具有用于至少一个半导体元件的安装位置，并且第一侧具有电连接到第二侧上的位置的多个位置。 在位置处设置多个导电互连件，每个导电互连件具有附接在该位置处的第一端和与衬底间隔开的第二端，并且密封剂部分地封装多个互连件，并且具有位于第一平面中的表面。 第二端位于与衬底第一侧相对的第一平面的侧面上，密封剂中的环形空间围绕多个导电互连件中的每一个，并且环形空间具有位于第一平面和衬底之间的底部 第一面。 也是制造这种半导体器件的方法。

公开(公告)号：US20250118645A1

公开(公告)日：2025-04-10

申请号：US18987457

申请日：2024-12-19

Applicant: QUALCOMM Incorporated

Inventor： Jihong Choi ,  Giridhar Nallapati ,  William Stone ,  Jianwen Xu ,  Jonghae Kim ,  Periannan Chidambaram ,  Ahmer Syed

IPC: H01L23/498 ,  H01L21/48 ,  H10D1/68

Abstract: Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate and related fabrication methods. The embedded capacitor can be coupled to a power distribution network (PDN) to provide decoupling capacitance to reduce current-resistance (IR) drop. The RDL substrate is disposed between the IC chip(s) and the package substrate to minimize distance between the embedded capacitor(s) and the IC chip(s) to reduce the parasitic inductance in the PDN, thus reducing PDN noise. With the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections between the package substrate and the IC chip(s). In this regard, the RDL substrate includes an outer RDL layer adjacent to the IC chip(s) to support small pitch metal interconnects as well as provide fan-out capability. This provides enhanced connectivity compatibility with higher-density die interconnect IC chips while also supporting a closer located embedded capacitor in the PDN.

公开(公告)号：US20140339712A1

公开(公告)日：2014-11-20

申请号：US13898427

申请日：2013-05-20

Applicant: QUALCOMM Incorporated

Inventor： Reynante Tamunan Alvarado ,  Lizabeth Ann Keser ,  Jianwen Xu

IPC: H01L23/00

CPC classification number: H01L21/561 ,  B23K26/364 ,  B23K26/389 ,  B23K26/40 ,  B23K2103/172 ,  H01L21/31127 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/3185 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2924/00

Abstract: Some implementations provide a semiconductor device that includes a substrate, several metal and dielectric layers coupled to the substrate, and a pad coupled to one of the several metal layers. The semiconductor device also includes a first metal layer coupled to the pad and an under bump metallization layer coupled to the first metal redistribution layer. The semiconductor device further includes a mold layer covering a first surface of the semiconductor device and at least a side portion of the semiconductor device. In some implementations, the mold layer is an epoxy layer. In some implementations, the first surface of the semiconductor device is the top side of the semiconductor device. In some implementations, the mold layer covers the at least side portion of the semiconductor device such that a side portion of at least one of the several metal layers and dielectric layers is covered with the mold layer.

Abstract translation: 一些实施方案提供了一种半导体器件，其包括衬底，耦合到衬底的几个金属和电介质层，以及耦合到几个金属层之一的焊盘。 半导体器件还包括耦合到焊盘的第一金属层和耦合到第一金属再分配层的凸块下金属化层。 半导体器件还包括覆盖半导体器件的第一表面和至少半导体器件的侧部的模层。 在一些实施方案中，模制层是环氧树脂层。 在一些实施方案中，半导体器件的第一表面是半导体器件的顶侧。 在一些实施方案中，模具层覆盖半导体器件的至少侧面部分，使得多个金属层和电介质层中的至少一个的侧部被模具层覆盖。

公开(公告)号：US08841168B2

公开(公告)日：2014-09-23

申请号：US13890625

申请日：2013-05-09

Applicant: QUALCOMM Incorporated

Inventor： Mark Wendell Schwarz ,  Jianwen Xu

IPC: H01L21/02 ,  H01L21/12 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H05K3/34 ,  H01L21/00

CPC classification number: H01L24/11 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/49811 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3436 ,  Y02P70/613 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate having a first side and a second side, the second side having a mounting location for at least one semiconductor element, and the first side having a plurality of locations electrically connected to locations on the second side. A plurality of electrically conductive interconnects are provided at the locations, each having a first end attached at the location and a second end spaced from the substrate, and an encapsulant partially encapsulates the plurality of interconnects and has a surface lying in a first plane. The second ends are located on the side of the first plane opposite from the substrate first side, an annular space in the encapsulant surrounds each of the plurality of electrically conductive interconnects, and the annular space has a bottom located between the first plane and the substrate first side. Also a method for making such a semiconductor device.

Abstract translation: 半导体器件包括具有第一侧和第二侧的衬底，第二侧具有用于至少一个半导体元件的安装位置，并且第一侧具有电连接到第二侧上的位置的多个位置。 在位置处设置多个导电互连件，每个导电互连件具有附接在该位置处的第一端和与衬底间隔开的第二端，并且密封剂部分地封装多个互连件，并且具有位于第一平面中的表面。 第二端位于与衬底第一侧相对的第一平面的侧面上，密封剂中的环形空间围绕多个导电互连件中的每一个，并且环形空间具有位于第一平面和衬底之间的底部 第一面。 也是制造这种半导体器件的方法。