公开(公告)号：US11594491B2

公开(公告)日：2023-02-28

申请号：US17245903

申请日：2021-04-30

Applicant: QUALCOMM Incorporated

Inventor： Li-Sheng Weng ,  Hong Bok We

IPC: H01L23/538 ,  H01L23/13 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31

Abstract: Disclosed is an apparatus including a molded multi-die high density interconnect including: a bridge die having a first plurality of interconnects and second plurality of interconnects. The apparatus also includes a first die having a first plurality of contacts and a second plurality of contacts, where the second plurality of contacts is coupled to the first plurality of interconnects of the bridge die. The apparatus also includes a second die having a first plurality of contacts and a second plurality of contacts, where the second plurality of contacts is coupled to the second plurality of interconnects of the bridge die. The coupled second plurality of contacts and interconnects have a smaller height than the first plurality of contacts of the first die and second die.

公开(公告)号：US11605594B2

公开(公告)日：2023-03-14

申请号：US17017361

申请日：2020-09-10

Applicant: QUALCOMM Incorporated

Inventor： Ryan Lane ,  Li-Sheng Weng ,  Charles David Paynter ,  Eric David Foronda

IPC: H01L23/538 ,  H01L25/00 ,  H01L25/065

Abstract: A package comprising a substrate, an integrated device, and an interconnect integrated device. The substrate includes a first surface and a second surface. The substrate further includes a plurality of interconnects. The integrated device is coupled to the substrate. The interconnect integrated device is coupled to a surface of the substrate. The integrated device, the interconnect integrated device and the substrate are configured to provide an electrical path for an electrical signal of the integrated device, that travels through at least the substrate, then through the interconnect integrated device and back through the substrate.

公开(公告)号：US11139224B2

公开(公告)日：2021-10-05

申请号：US16704789

申请日：2019-12-05

Applicant: QUALCOMM Incorporated

Inventor： Chaoqi Zhang ,  Rajneesh Kumar ,  Li-Sheng Weng ,  Darryl Sheldon Jessie ,  Suhyung Hwang ,  Jeahyeong Han ,  Xiaoming Chen ,  Jaehyun Yeon

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/56 ,  H01L21/67 ,  H01L23/31

Abstract: A package that includes a substrate having a routing region and a non-routing region along a periphery of the substrate. The non-routing region includes a plurality of vias configured as a shield. The package includes an integrated device coupled to the substrate, and an encapsulation layer located over the substrate such that the encapsulation layer encapsulates the integrated device.

公开(公告)号：US11784157B2

公开(公告)日：2023-10-10

申请号：US17339830

申请日：2021-06-04

Applicant: QUALCOMM Incorporated

Inventor： Li-Sheng Weng ,  Charles David Paynter ,  Ryan Lane ,  Jianwen Xu ,  William Stone

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L24/73 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L24/20 ,  H01L24/24 ,  H01L25/105 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17163 ,  H01L2224/2105 ,  H01L2224/24145 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A package comprising a first integrated device comprising a plurality of first pillar interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a metallization portion located over the first integrated device and the encapsulation layer, wherein the metallization portion includes at least one passivation layer and a plurality of metallization layer interconnects, wherein the plurality of first pillar interconnects is coupled to the plurality of metallization layer interconnects; and a second integrated device comprising a plurality of second pillar interconnects, wherein the second integrated device is coupled to the plurality of metallization layer interconnects through a plurality of second pillar interconnects and a plurality of solder interconnects.

公开(公告)号：US11676922B2

公开(公告)日：2023-06-13

申请号：US16665883

申请日：2019-10-28

Applicant: QUALCOMM Incorporated

Inventor： Li-Sheng Weng ,  Yue Li ,  Yangyang Sun

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/10122 ,  H01L2224/1182 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/14133 ,  H01L2924/3025

Abstract: An integrated device that includes a substrate, an interconnect portion and an interconnect structure. The interconnect portion is located over the substrate. The interconnect portion includes a plurality of interconnects and at least one dielectric layer. The interconnect structure is located over the interconnect portion. The interconnect structure includes an inner interconnect, a dielectric layer coupled to the inner interconnect, and an outer conductive layer coupled to the dielectric layer. The outer conductive layer is configured to operate as a shield for the inner interconnect.

公开(公告)号：US11380613B2

公开(公告)日：2022-07-05

申请号：US16888516

申请日：2020-05-29

Applicant: QUALCOMM Incorporated

Inventor： Yue Li ,  Li-Sheng Weng ,  Yangyang Sun

IPC: H01L23/50 ,  H01L23/00

Abstract: An integrated circuit (IC) package is described. The IC package includes a die, having a pad layer structure on back-end-of-line layers on a substrate. The die also includes a metallization routing layer on the pad layer structure, and a first under bump metallization layer on the metallization routing layer. The IC package also includes a patterned seed layer on a surface of the die to contact the first under bump metallization layer. The IC package further includes a first package bump on the first under bump metallization layer.

公开(公告)号：US20220199547A1

公开(公告)日：2022-06-23

申请号：US17127750

申请日：2020-12-18

Applicant: QUALCOMM Incorporated

Inventor： Li-Sheng Weng ,  Yu-Chih Chen ,  Chaoqi Zhang

IPC: H01L23/552 ,  H01L23/00

Abstract: Fan-out wafer-level packaging (FOWLP) integrated circuits (ICs) employing electro-magnetic (EM) interference (EMI) shield structure in fan out area for EMI shielding, and related fabricating methods are disclosed. The IC includes a semiconductor die (“IC die”) that is bonded to the reconstituted carrier wafer such that a fan-out area is provided between adjacent IC dies to provide area for fan-out interconnects to provide additional die interconnections to the IC die. In exemplary aspects, the IC includes an EMI shield that includes vias formed in an un-used area in fan-out area adjacent to the IC die electrically that are otherwise unused for input/output (I/O) signal interconnects for coupling I/O signals to the IC die. The EMI shield is electrically coupled to a ground node of the IC die to provide an effective EMI shield to block or attenuate unwanted EM noise propagated from the IC die outside the IC.