公开(公告)号：US20160358928A1

公开(公告)日：2016-12-08

申请号：US14729553

申请日：2015-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/115 ,  H01L23/528 ,  H01L21/768 ,  H01L29/423

CPC classification number: H01L27/11519 ,  H01L21/28273 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76883 ,  H01L23/5283 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7831 ,  H01L29/788 ,  H01L29/7881

Abstract: The present disclosure relates to a flash memory device, and associated methods. In some embodiments, the flash memory device has a gate stack with a control gate separated from a floating gate by a control gate dielectric. An erase gate disposed on a first side of the gate stack. A word line is disposed on a second side of the gate stack that is opposite the first side. The word line has a height that monotonically increases from an outer side opposite to the gate stack to an inner side closer to the gate stack. The shape of the word line optimizes the contact resistance of the word line and allows for an overlying cap spacer formed on the word line to be well defined, which can provide more reliable read/write operations and/or better performance.

Abstract translation: 本公开涉及闪存器件及相关方法。 在一些实施例中，闪存器件具有栅极堆叠，其中控制栅极通过控制栅极电介质与浮动栅极分离。 设置在栅极堆叠的第一侧上的擦除栅极。 字线布置在栅堆叠的与第一侧相对的第二侧上。 字线具有从与栅极堆叠相反的外侧单个增加到更靠近栅极堆叠的内侧的高度。 字线的形状优化了字线的接触电阻，并允许形成在字线上的上覆帽间隔被良好地限定，这可以提供更可靠的读/写操作和/或更好的性能。

公开(公告)号：US09514820B2

公开(公告)日：2016-12-06

申请号：US14547199

申请日：2014-11-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois Tailliet

IPC: G11C16/00 ,  G11C16/04 ,  G11C16/14 ,  H01L27/115 ,  G11C29/08 ,  G11C16/08 ,  G11C16/10 ,  G11C29/50

CPC classification number: G11C16/0483 ,  G11C16/0441 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C29/08 ,  G11C29/50004 ,  H01L27/11519 ,  H01L27/11524

Abstract: An integrated circuit memory includes memory cells arranged in an array with rows and columns, each column including a first bit line and a second bit line. Each memory cell is formed by: a first select transistor with a first source-drain path; a second select transistor with a second source-drain path; a first floating gate transistor with a third source-drain path; and a second floating gate transistor with a fourth source-drain path. The first, second, third and fourth source-drain paths are coupled in series between the first bit line and the second bit line. The word line for each row of the memory is coupled to the gate terminals of the first and second select transistors. The control gate line for each row in coupled to the gate terminals of the first and second floating gate transistors.

Abstract translation: 集成电路存储器包括以行和列排列成阵列的存储单元，每列包括第一位线和第二位线。 每个存储单元由以下部分形成：具有第一源极 - 漏极路径的第一选择晶体管; 具有第二源极 - 漏极路径的第二选择晶体管; 具有第三源极 - 漏极路径的第一浮栅晶体管; 以及具有第四源极 - 漏极路径的第二浮栅晶体管。 第一，第二，第三和第四源极 - 漏极路径串联耦合在第一位线和第二位线之间。 存储器的每行的字线被耦合到第一和第二选择晶体管的栅极端子。 耦合到第一和第二浮栅晶体管的栅极端的每行的控制栅极线。

公开(公告)号：US09508731B2

公开(公告)日：2016-11-29

申请号：US14667331

申请日：2015-03-24

Applicant: Intel Corporation

Inventor： Graham Richard Wolstenholme

IPC: H01L27/115

CPC classification number: H01L27/11551 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for providing a 3D memory array apparatus. In one embodiment, the apparatus may comprise a substantially hexagonal arrangement having seven pillars disposed in a die in a repeating pattern. The arrangement may include first and second pillars disposed at a pillar pitch from each other in a first row; third, fourth, and fifth pillars disposed at the pillar pitch from each other in a second row; and sixth and seventh pillar disposed at the pillar pitch from each other in a third row and shifted relative to the first and second pillars respectively by a quarter of the pillar pitch in a direction that is substantially orthogonal to bitlines disposed in the die. Each pillar in the arrangement may be electrically coupled with a different bitline. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于提供3D存储器阵列装置的技术和配置。 在一个实施例中，该装置可以包括基本上六边形的布置，其具有以重复图案设置在模具中的七个支柱。 该布置可以包括在第一排中彼此以柱间距设置的第一和第二柱; 第三柱，第四柱和第五柱，在第二排中彼此以柱间距排列; 第六柱和第七柱以第三排彼此相互间隔设置，并且相对于第一和第二柱相对于基本上与设置在模具中的位线正交的方向分别移动四分之一的柱间距。 该装置中的每个支柱可以与不同的位线电耦合。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160322373A1

公开(公告)日：2016-11-03

申请号：US15205954

申请日：2016-07-08

Applicant: Kabushiki Kaisha Toshiba

Inventor： Wataru SAKAMOTO ,  Ryota Suzuki ,  Tatsuya Okamoto ,  Tatsuya Kato ,  Fumitaka Arai

IPC: H01L27/115 ,  G11C16/24 ,  G11C16/30 ,  G11C16/04 ,  H01L29/06 ,  H01L23/528

CPC classification number: H01L27/11556 ,  G11C16/0408 ,  G11C16/0483 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11582 ,  H01L29/0649 ,  H01L29/66825 ,  H01L29/7926

Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.

Abstract translation: 半导体存储器件包括两个第一电极膜，第一列和第二绝缘膜。 两个第一电极膜沿第一方向延伸并且在第二方向上彼此分离。 第一列设置在两个第一电极膜之间，并且具有多个第一构件和多个绝缘构件。 第一构件和每个绝缘构件中的每一个在第一方向上交替布置。 多个第一构件中的一个具有设置在半导体柱和第二电极膜之间的半导体柱，第二电极膜和第一绝缘膜。 半导体柱，第一绝缘膜和第二电极膜沿第二方向排列。 第二绝缘膜设置在第一列和两个第一电极膜之一之间。

公开(公告)号：US09478560B2

公开(公告)日：2016-10-25

申请号：US14940137

申请日：2015-11-12

Applicant: Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

Inventor： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

IPC: G11C11/34 ,  G11C16/04 ,  H01L27/115 ,  H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/06 ,  H01L29/41

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/0676 ,  H01L29/413 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

Abstract: Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.

公开(公告)号：US09478495B1

公开(公告)日：2016-10-25

申请号：US14922516

申请日：2015-10-26

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Jayavel Pachamuthu ,  Peter Rabkin ,  Jilin Xia ,  Christopher Petti

IPC: H01L23/52 ,  H01L23/532 ,  H01L29/16 ,  H01L29/04 ,  H01L29/423 ,  H01L21/768 ,  H01L21/324 ,  H01L29/792 ,  H01L29/66 ,  H01L27/115 ,  H01L29/788 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/53223 ,  H01L21/324 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76867 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53204 ,  H01L23/5329 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A low-stress contact via structure for a device employing an alternating stack of insulating layers and electrically conductive layers over a substrate can be formed by forming a trench extending to the substrate through the alternating stack. After formation of an insulating spacer and a diffusion barrier layer, a remaining volume of the trench can be filled with a combination of an aluminum portion and a non-metallic material portion to form a contact via structure. The non-metallic material portion can include a semiconductor material portion or a dielectric material portion, and can prevent reflow of the aluminum portion and generation of a cavity in subsequent thermal processes. If a semiconductor material portion is employed, the aluminum portion and the semiconductor material portion can exchange places during a metal induced crystallization anneal process of the semiconductor material.

Abstract translation: 可以通过形成通过交替堆叠延伸到衬底的沟槽来形成用于在衬底上使用绝缘层和导电层的交替堆叠的器件的低应力接触通孔结构。 在形成绝缘间隔物和扩散阻挡层之后，可以用铝部分和非金属材料部分的组合填充沟槽的剩余体积以形成接触通孔结构。 非金属材料部分可以包括半导体材料部分或电介质材料部分，并且可以防止铝部分的回流和随后的热处理中的空腔的产生。 如果使用半导体材料部分，则在半导体材料的金属诱导结晶退火工艺期间，铝部分和半导体材料部分可以交换位置。

公开(公告)号：US09472500B2

公开(公告)日：2016-10-18

申请号：US14678650

申请日：2015-04-03

Applicant: SK hynix Inc.

Inventor： Jung Hoon Kim ,  Sung Kun Park ,  Nam Yoon Kim

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L27/11524 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11519 ,  H01L29/0688 ,  H01L29/42328 ,  H01L29/788 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A nonvolatile memory device includes an active region extending in a first direction, a first single-layered gate intersecting the active region and extending in a second direction, a second single-layered gate intersecting the active region and extending in the second direction, and a selection gate intersecting the active region. The selection gate includes a first selection gate main line and a second selection gate main line that intersect the active region to be parallel with the first and second single-layered gates, a selection gate interconnection line that connects a first end of the first selection gate main line to a first end of the second selection gate main line, and a selection gate extension that extends from a portion of the selection gate interconnection line to be disposed between first ends of the first and second single-layered gates.

Abstract translation: 非易失性存储器件包括沿着第一方向延伸的有源区域，与有源区域相交并且沿第二方向延伸的第一单层栅极，与有源区域相交且沿第二方向延伸的第二单层栅极，以及 选择门与有源区相交。 选择栅极包括与第一和第二单层栅极平行的有源区相交的第一选择栅极主线和第二选择栅极主线，连接第一选择栅极的第一端的选择栅极互连线 主线延伸到第二选择栅极主线的第一端，以及选择栅极延伸部，其从选择栅极互连线的一部分延伸，以设置在第一和第二单层栅极的第一端之间。

公开(公告)号：US09472289B2

公开(公告)日：2016-10-18

申请号：US15001361

申请日：2016-01-20

Applicant: Renesas Electronics Corporation

Inventor： Hideaki Yamakoshi

IPC: G11C16/04 ,  G11C16/10 ,  H01L27/115 ,  G11C16/26 ,  G11C16/14 ,  H01L27/02 ,  H01L29/788

CPC classification number: G11C16/10 ,  G11C16/0441 ,  G11C16/14 ,  G11C16/26 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11546 ,  H01L27/11558

Abstract: In order to reduce a chip area of a semiconductor device having a non-volatile memory, a configuration is adopted, in which a length in a second direction of a capacity electrode of an element for writing/erasing data is made smaller than both a length in the second direction of a gate electrode of an element for reading data formed by part of the same floating electrode and a length in the second direction of a capacity electrode of a capacitive element. Herein, by recessing, of the side surfaces of the capacity electrode of the element for writing/erasing data, the side surface on the side opposite to the capacity electrode of the other element for writing/erasing data adjacent to the former element for writing/erasing data, a length in the second direction of an active region where the element for writing/erasing data is arranged is reduced.

Abstract translation: 为了减少具有非易失性存储器的半导体器件的芯片面积，采用这样的结构，其中用于写入/擦除数据的元件的电容电极的第二方向上的长度小于长度 在用于读取由相同浮动电极的一部分形成的数据和电容元件的电容电极的第二方向上的长度的元件的栅电极的第二方向上。 在这里，通过凹入用于写入/擦除数据的元件的电容电极的侧表面，与用于写入/擦除数据的另一元件的电容电极相反的一侧的侧表面与前一个写/ 擦除数据时，减少了用于写/擦除数据的元素的有效区域的第二方向上的长度。

公开(公告)号：US20160300847A1

公开(公告)日：2016-10-13

申请号：US15185020

申请日：2016-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wanit MANOROTKUL ,  Joong-han SHIN ,  Bong-jin KUH ,  Han-mei CHOI ,  Dmitry MIKULIK

IPC: H01L27/115 ,  H01L21/3205 ,  H01L21/02 ,  H01L23/528

CPC classification number: H01L27/11575 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02675 ,  H01L21/32055 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: An IC device includes a polycrystalline silicon thin film interposed between a first level semiconductor circuit and a second level semiconductor circuit which are formed on a substrate and disposed to vertically overlap each other. The polycrystalline silicon thin film includes at least one silicon single crystal. The at least one silicon single crystal includes a flat horizontal portion, which provides an active region of the second level semiconductor device, and a pin-shaped protruding portion protruding from the flat horizontal portion toward the first level semiconductor device.

公开(公告)号：US20160293539A1

公开(公告)日：2016-10-06

申请号：US15067833

申请日：2016-03-11

Applicant: JOYOUNG PARK ,  SEOK-WON LEE ,  SEONGJUN SEO

Inventor： JOYOUNG PARK ,  SEOK-WON LEE ,  SEONGJUN SEO

IPC: H01L23/528 ,  H01L27/24 ,  H01L23/522 ,  H01L27/115

CPC classification number: H01L27/2481 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

Abstract: A three-dimensional semiconductor device is provided as follows. A substrate includes a contact region, a dummy region, and a cell array region. A stack structure includes electrodes vertically stacked on the substrate. The electrodes are stacked to have a first stepwise structure on the contact region and a second stepwise structure in the dummy region. Ends of at least two adjacent electrodes in the second stepwise structure have first sidewalls vertically aligned so that horizontal positions of the first sidewalls are substantially the same.

Abstract translation: 如下提供三维半导体器件。 基板包括接触区域，虚拟区域和单元阵列区域。 堆叠结构包括垂直堆叠在基板上的电极。 电极堆叠成在接触区域上具有第一分级结构，在虚拟区域中具有第二阶梯结构。 第二阶梯结构中的至少两个相邻电极的端部具有垂直对准的第一侧壁，使得第一侧壁的水平位置基本相同。