知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

507 条记录 (耗时 0.028 秒)

    Metal oxide layered structure and methods of forming the same
    95.
    发明授权
    Metal oxide layered structure and methods of forming the same 有权

    公开(公告)号：US11443957B2

    公开(公告)日：2022-09-13

    申请号：US16876938

    申请日：2020-05-18

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Jing-Cheng Lin ,  Cheng-Lin Huang

    IPC分类号： H01L21/321 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/768 ,  H01L23/532 ,  H01L23/498 ,  H01L25/065 ,  H01L23/525

    摘要： Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 Å. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.

    Through-substrate vias with improved connections
    96.
    发明授权
    Through-substrate vias with improved connections 有权

    公开(公告)号：US11296011B2

    公开(公告)日：2022-04-05

    申请号：US16459387

    申请日：2019-07-01

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Jing-Cheng Lin ,  Ku-Feng Yang

    IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/00

    摘要： A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.

    Semiconductor device
    98.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11062987B2

    公开(公告)日：2021-07-13

    申请号：US16846993

    申请日：2020-04-13

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Jing-Cheng Lin ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Po-Hao Tsai

    IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48

    摘要： A semiconductor device includes a substrate, a first redistribution layer (RDL) over a first side of the substrate, one or more semiconductor dies over and electrically coupled to the first RDL, and an encapsulant over the first RDL and around the one or more semiconductor dies. The semiconductor device also includes connectors attached to a second side of the substrate opposing the first side, the connectors being electrically coupled to the first RDL. The semiconductor device further includes a polymer layer on the second side of the substrate, the connectors protruding from the polymer layer above a first surface of the polymer layer distal the substrate. A first portion of the polymer layer contacting the connectors has a first thickness, and a second portion of the polymer layer between adjacent connectors has a second thickness smaller than the first thickness.