公开(公告)号：US20180204902A1

公开(公告)日：2018-07-19

申请号：US15582963

申请日：2017-05-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Li Huang ,  Chi-Cheng Chen ,  Hon-Lin Huang ,  Chien-Chih Chou ,  Chin-Yu Ku ,  Chen-Shien Chen

IPC: H01L49/02 ,  H01L21/3213 ,  H01F41/04 ,  H01F27/28

CPC classification number: H01L28/10 ,  H01F27/2804 ,  H01F41/041 ,  H01L21/32134 ,  H01L21/32139 ,  H01L23/5227 ,  H01L23/645 ,  H01L27/222 ,  H01L2924/1206

Abstract: A method of manufacturing a semiconductor device and the semiconductor device are provided in which a plurality of layers with cobalt-zirconium-tantalum are formed over a semiconductor substrate, the plurality of layers are patterned, and multiple dielectric layers and conductive materials are deposited over the CZT material. Another layer of CZT material encapsulates the conductive material.

公开(公告)号：US10008479B2

公开(公告)日：2018-06-26

申请号：US15401851

申请日：2017-01-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Wen Hsiao ,  Chen-Shien Chen ,  Wei Sen Chang ,  Shou-Cheng Hu

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/538 ,  H01L23/64 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/522 ,  H01L21/683 ,  H01L23/31 ,  H01L23/48 ,  H01L23/528 ,  H01L23/50

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/538 ,  H01L23/5389 ,  H01L23/64 ,  H01L24/19 ,  H01L24/24 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00

Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.

公开(公告)号：US09966346B2

公开(公告)日：2018-05-08

申请号：US14828147

申请日：2015-08-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Guan-Yu Chen ,  Yu-Wei Lin ,  Yu-Jen Tseng ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L24/02 ,  H01L21/4853 ,  H01L21/76885 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02125 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/0401 ,  H01L2224/05114 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13551 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13686 ,  H01L2224/1369 ,  H01L2224/14051 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/81007 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/81895 ,  H01L2224/8192 ,  H01L2224/81948 ,  H01L2225/06513 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/35 ,  Y10T29/49144 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

公开(公告)号：US09953939B2

公开(公告)日：2018-04-24

申请号：US15356316

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Liang Lin ,  Yu-Jen Tseng ,  Chang-Chia Huang ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L21/48

CPC classification number: H01L24/02 ,  H01L21/4853 ,  H01L21/76885 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02125 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/0401 ,  H01L2224/05114 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13551 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13686 ,  H01L2224/1369 ,  H01L2224/14051 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/81007 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/81895 ,  H01L2224/8192 ,  H01L2224/81948 ,  H01L2225/06513 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/35 ,  Y10T29/49144 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar has a pillar width, and the UBM width is greater than the pillar width.

公开(公告)号：US09935081B2

公开(公告)日：2018-04-03

申请号：US14464509

申请日：2014-08-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo Lung Pan ,  Yu-Feng Chen ,  Chen-Shien Chen ,  Mirng-Ji Lii

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/768

CPC classification number: H01L25/0655 ,  H01L21/4853 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/24 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/13009 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/8203 ,  H01L2224/82105 ,  H01L2224/92125 ,  H01L2224/92133 ,  H01L2224/92242 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a substrate, and adhering a first semiconductor device. Chip stacks are formed by providing a plurality of semiconductor devices and bonding them to the substrate and the first semiconductor device. At least one of the provided semiconductor devices is physically connected to both the substrate and the first semiconductor device it is stack on. Other semiconductor devices may stacked by forming conductive channels in the first semiconductor device, and placing the other semiconductor devices in physical contact with the first semiconductor device and the conductive channels.

公开(公告)号：US20170372976A1

公开(公告)日：2017-12-28

申请号：US15700830

申请日：2017-09-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hua Chen ,  Chen-Shien Chen ,  Ching-Wen Hsiao

IPC: H01L21/66 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L23/31 ,  H01L23/528

CPC classification number: H01L22/32 ,  H01L22/34 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13083 ,  H01L2224/1403 ,  H01L2224/14133 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost.

公开(公告)号：US09773749B2

公开(公告)日：2017-09-26

申请号：US15354731

申请日：2016-11-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo Lung Pan ,  Ching-Wen Hsiao ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/82 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/13 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00

Abstract: Various embodiments of mechanisms for forming a die package using a compressive dielectric layer to contact and to surround through substrate vias (TSVs) in the die package are provided. The compressive dielectric layer reduces or eliminates bowing of the die package. As a result, the risk of broken redistribution layer (RDL) due to bowing is reduced or eliminated. In addition, the compressive dielectric layer, which is formed between the conductive TSV columns and surrounding molding compound, improves the adhesion between the conductive TSV columns and the molding compound. Consequently, the reliability of the die package is improved.

公开(公告)号：US09761503B2

公开(公告)日：2017-09-12

申请号：US14728608

申请日：2015-06-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hua Chen ,  Chen-Shien Chen ,  Ching-Wen Hsiao

IPC: H01L23/58 ,  H01L21/66 ,  H01L23/31 ,  H01L23/528 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L22/32 ,  H01L22/34 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/528 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13083 ,  H01L2224/1403 ,  H01L2224/14133 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost.

公开(公告)号：US09748188B2

公开(公告)日：2017-08-29

申请号：US14934634

申请日：2015-11-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Cheng Kuo ,  Chita Chuang ,  Chen-Shien Chen ,  Yao-Chun Chuang

IPC: H01L23/48 ,  H01L25/10 ,  H01L23/49 ,  H01L29/00 ,  H01L23/00 ,  H01L23/488 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L23/488 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05015 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/13014 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/141 ,  H01L2224/16104 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints.

公开(公告)号：US09646923B2

公开(公告)日：2017-05-09

申请号：US13719019

申请日：2012-12-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Jen Tseng ,  Yen-Liang Lin ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Mirng-Ji Lii

IPC: H01L23/498 ,  H01L23/528 ,  H01L23/00 ,  H01L23/488 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/15 ,  H01L21/02118 ,  H01L21/0273 ,  H01L21/283 ,  H01L21/44 ,  H01L21/47 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3192 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/02333 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13686 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/73104 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2224/8182 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a semiconductor device includes a substrate and conductive traces disposed over the substrate. Each of the conductive traces has a bottom region proximate the substrate and a top region opposite the bottom region. The top region has a first width and the bottom region has a second width. The second width is greater than the first width.