公开(公告)号：US20190164805A1

公开(公告)日：2019-05-30

申请号：US16191338

申请日：2018-11-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Lei-Chun Chou ,  Chih-Liang Chen ,  Jiann-Tyng Tzeng ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Charles Chew-Yuen Young

IPC分类号： H01L21/74 ,  H01L21/762 ,  H01L29/66 ,  H01L23/535 ,  H01L27/11

摘要： A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.

公开(公告)号：US20190067290A1

公开(公告)日：2019-02-28

申请号：US15691974

申请日：2017-08-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Shih-Ming Chang ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Yu-Jung Chang ,  Guo-Huei Wu

IPC分类号： H01L27/108 ,  H01L21/768 ,  H01L23/522 ,  H01L27/02 ,  H01L23/528

CPC分类号： H01L27/10823 ,  H01L21/76897 ,  H01L23/522 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/10808 ,  H01L27/10826 ,  H01L27/10829

摘要： An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

公开(公告)号：US20180197750A1

公开(公告)日：2018-07-12

申请号：US15912177

申请日：2018-03-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Ming Chang ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Chung-Ju Lee ,  Tien-I Bao ,  Shau-Lin Shue

IPC分类号： H01L21/321 ,  H01L23/522 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/311

CPC分类号： H01L21/3212 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2221/1063

摘要： An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.

公开(公告)号：US09911623B2

公开(公告)日：2018-03-06

申请号：US14970242

申请日：2015-12-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Ming Chang ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Chung-Ju Lee ,  Tien-I Bao ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L21/321 ,  H01L21/311 ,  H01L21/3105 ,  H01L23/522

CPC分类号： H01L21/3212 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76808 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226

摘要： A method includes forming a trench that is partially filled with a first metal material, the trench being formed within a first Interlayer Dielectric (ILD) layer, filling a remaining portion of the trench with a sacrificial material, depositing a buffer layer on the first ILD layer, patterning the buffer layer to form a hole within the buffer layer to expose the sacrificial material, and removing the sacrificial material.

公开(公告)号：US20170372891A1

公开(公告)日：2017-12-28

申请号：US15698936

申请日：2017-09-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Ming Chang ,  Ming-Feng Shieh ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC分类号： H01L21/02 ,  G03F1/00 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/302 ,  H01L21/033 ,  G03F7/20 ,  H01L27/12 ,  H01L29/66

CPC分类号： H01L21/02071 ,  G03F1/144 ,  G03F7/70466 ,  H01L21/0337 ,  H01L21/302 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.

公开(公告)号：US09478636B2

公开(公告)日：2016-10-25

申请号：US14280196

申请日：2014-05-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Liang Chen ,  Chih-Ming Lai ,  Kam-Tou Sio ,  Ru-Gun Liu ,  Meng-Hung Shen ,  Chun-Hung Liou ,  Shu-Hui Sung ,  Charles Chew-Yuen Young

IPC分类号： G01R31/26 ,  H01L29/66 ,  H01L21/768 ,  H01L23/535 ,  H01L23/48 ,  H01L21/8234

CPC分类号： H01L23/5226 ,  H01L21/768 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/48 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/535 ,  H01L27/088 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66583 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor device and methods of forming the same. The semiconductor device includes a substrate having source/drain regions and a channel region between the source/drain regions; a gate structure over the substrate and adjacent to the channel region; source/drain contacts over the source/drain regions and electrically connecting to the source/drain regions; and a contact protection layer over the source/drain contacts. The gate structure includes a gate stack and a spacer. A top surface of the source/drain contacts is lower than a top surface of the spacer, which is substantially co-planar with a top surface of the contact protection layer. The contact protection layer prevents accidental shorts between the gate stack and the source/drain regions when gate vias are formed over the gate stack. Therefore, gate vias may be formed over any portion of the gate stack, even in areas that overlap the channel region from a top view.

摘要翻译： 提供一种半导体器件及其形成方法。 半导体器件包括具有源极/漏极区域和源极/漏极区域之间的沟道区域的衬底; 在衬底上并且与沟道区相邻的栅极结构; 源极/漏极接触，并且电连接到源极/漏极区域; 以及源/漏触点上的接触保护层。 栅极结构包括栅极堆叠和间隔物。 源极/漏极触点的顶表面低于间隔物的顶表面，该顶表面与接触保护层的顶表面基本上共面。 当栅极通孔形成在栅极堆叠上时，接触保护层防止栅极堆叠与源极/漏极区域之间的意外短路。 因此，即使在从顶视图与沟道区域重叠的区域中，也可以在栅极堆叠的任何部分上形成栅极通孔。

公开(公告)号：US20160293422A1

公开(公告)日：2016-10-06

申请号：US15174131

申请日：2016-06-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsong-Hua Ou ,  Ken-Hsien Hsieh ,  Shih-Ming Chang ,  Wen-Chun Huang ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC分类号： H01L21/033

CPC分类号： H01L21/0338 ,  H01L21/0274 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32139

摘要： The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.

摘要翻译： 本公开提供了在半导体衬底上图案化靶材料层的方法。 该方法包括以下步骤：使用第一子布局在目标材料层上形成间隔物特征，并使用第二子布局进行光刻图案化处理以形成第一特征。 第一特征的一部分在间隔物特征上延伸。 该方法还包括以下步骤：移除在间隔物特征上延伸的第一特征的部分并去除间隔物特征。 本文还提供了其它方法和相关的图案化半导体晶片。

公开(公告)号：US09362119B2

公开(公告)日：2016-06-07

申请号：US14262432

申请日：2014-04-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsong-Hua Ou ,  Ken-Hsien Hsieh ,  Shih-Ming Chang ,  Wen-Chun Huang ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC分类号： H01L21/311 ,  H01L21/027 ,  H01L21/321

CPC分类号： H01L21/0338 ,  H01L21/0274 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32139

摘要： The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of: forming a plurality of first features over the target material layer using a first sub-layout, with each first feature having sidewalls; forming a plurality of spacer features, with each spacer feature conforming to the sidewalls of one of the first features and having a spacer width; and forming a plurality of second features over the target material layer using a second sub-layout. The method further includes steps of removing the plurality of spacer features from around each first feature and patterning the target material layer using the plurality of first features and the plurality of second features. Other methods and associated patterned semiconductor wafers are also provided herein.

摘要翻译： 本公开提供了在半导体衬底上图案化靶材料层的方法。 该方法包括以下步骤：使用第一子布局在目标材料层上形成多个第一特征，每个第一特征具有侧壁; 形成多个间隔物特征，其中每个隔离物特征符合所述第一特征之一的侧壁并具有间隔物宽度; 以及使用第二子布局在所述目标材料层上形成多个第二特征。 该方法还包括以下步骤：从每个第一特征周围去除多个间隔物特征，并使用多个第一特征和多个第二特征对目标材料层进行图案化。 本文还提供了其它方法和相关的图案化半导体晶片。

公开(公告)号：US20160155639A1

公开(公告)日：2016-06-02

申请号：US15005861

申请日：2016-01-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Ming Chang ,  Ming-Feng Shieh ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC分类号： H01L21/033

CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/30625 ,  H01L21/3065

摘要： The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate, a patterning-target layer over the substrate, and a hard mask layer over the patterning-target layer; forming a first pattern in the hard mask layer; removing a trim portion from the first pattern in the hard mask layer to form a trimmed first pattern; forming a first resist layer over the hard mask layer; forming a main pattern in the first resist layer; and etching the patterning-target layer using the main pattern and the trimmed first pattern as etching mask elements to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting a first overlapping portion between the main pattern and the trimmed first pattern.

摘要翻译： 本公开提供了一种用于在半导体器件中形成图案的方法。 根据一些实施例，所述方法包括在所述图案化目标层上方提供衬底，所述衬底上的图案化目标层和硬掩模层; 在硬掩模层中形成第一图案; 从所述硬掩模层中的所述第一图案移除修剪部分以形成修剪的第一图案; 在所述硬掩模层上形成第一抗蚀剂层; 在第一抗蚀剂层中形成主图案; 并且使用主图案和修剪的第一图案作为蚀刻掩模元件来蚀刻图案化目标层，以在图案化目标层中形成最终图案。 在一些实施例中，最终图案包括主图案，减去主图案和经修剪的第一图案之间的第一重叠部分。

公开(公告)号：US09245763B2

公开(公告)日：2016-01-26

申请号：US14210032

申请日：2014-03-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Ming Chang ,  Ming-Feng Shieh ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC分类号： H01L21/44 ,  H01L21/308 ,  H01L21/02 ,  H01L21/306

CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/30625 ,  H01L21/3065

摘要： The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate, a patterning-target layer over the substrate, and a hard mask layer over the patterning-target layer; forming a first pattern in the hard mask layer; removing a trim portion from the first pattern in the hard mask layer to form a trimmed first pattern; forming a first resist layer over the hard mask layer; forming a main pattern in the first resist layer; and etching the patterning-target layer using the main pattern and the trimmed first pattern as etching mask elements to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting a first overlapping portion between the main pattern and the trimmed first pattern.

摘要翻译： 本公开提供了一种用于在半导体器件中形成图案的方法。 根据一些实施例，所述方法包括在所述图案化目标层上方提供衬底，所述衬底上的图案化目标层和硬掩模层; 在硬掩模层中形成第一图案; 从所述硬掩模层中的所述第一图案移除修剪部分以形成修剪的第一图案; 在所述硬掩模层上形成第一抗蚀剂层; 在第一抗蚀剂层中形成主图案; 并且使用主图案和修剪的第一图案作为蚀刻掩模元件来蚀刻图案化目标层，以在图案化目标层中形成最终图案。 在一些实施例中，最终图案包括主图案，减去主图案和经修剪的第一图案之间的第一重叠部分。