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    Method of forming features with various dimensions
    4.
    发明授权
    Method of forming features with various dimensions 有权

    公开(公告)号：US09728407B2

    公开(公告)日：2017-08-08

    申请号：US14983743

    申请日：2015-12-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Ken-Hsien Hsieh ,  Chi-Cheng Hung ,  Chih-Ming Lai ,  Wei-Liang Lin ,  Chun-Kuang Chen ,  Ru-Gun Liu

    IPC分类号： H01L21/033

    CPC分类号： H01L21/0337 ,  H01L21/31144 ,  H01L21/32139

    摘要： A method of fabricating a semiconductor device is disclosed. The method includes forming mandrels over a material layer and forming spacers along sidewalls of mandrels, forming a patterned hard mask to cover a first region, depositing a filling layer in a second region while the patterned hard mask covers the first region. A space between two adjacent spacers in the second region is filled in by the filling layer. The method also includes recessing the filling layer to form a filling block in the space between two adjacent spacers in the second region, removing the patterned hard mask, removing mandrels and etching the material layer by using spacers and the filling block as an etch mask to form material features in the first region and the second region, respectively.

    Method of determining whether a layout is colorable
    5.
    发明授权
    Method of determining whether a layout is colorable 有权
    确定布局是否可着色的方法

    公开(公告)号：US09390223B2

    公开(公告)日：2016-07-12

    申请号：US14872338

    申请日：2015-10-01

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Wen-Li Cheng ,  Ming-Hui Chih ,  Chia-Ping Chiang ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Wen-Chun Huang ,  Ru-Gun Liu

    IPC分类号： G06F17/50 ,  G03F1/00

    CPC分类号： G06F17/5081 ,  G03F1/00 ,  G03F1/70 ,  G03F7/70283 ,  G03F7/70433 ,  G03F7/70466

    摘要： A method of determining whether a layout is colorable includes assigning nodes to polygon features of the layout. The method includes designating nodes as being adjacent nodes for nodes separated by less than a minimum pitch. The method includes iteratively removing nodes having less than three adjacent nodes from consideration to identify a node arrangement, wherein all nodes in the node arrangement have at least three adjacent nodes. The method includes determining whether the layout is colorable based on the node arrangement. Determining whether the layout is colorable includes independently assessing each internal node of node arrangement to determine whether each internal node of the node arrangement is colorable. The method includes generating a colored layout design for fabrication of the semiconductor device if each internal node of the node arrangement is colorable; and modifying the layout if at least one internal node of the node arrangement is not colorable.

    摘要翻译： 确定布局是否可着色的方法包括将节点分配给布局的多边形特征。 该方法包括将节点指定为以小于最小间距分开的节点的相邻节点。 该方法包括从考虑中迭代地去除具有少于三个相邻节点的节点以识别节点布置，其中节点布置中的所有节点具有至少三个相邻节点。 该方法包括基于节点布置确定布局是否可着色。 确定布局是否可着色包括独立地评估节点布置的每个内部节点以确定节点布置的每个内部节点是否是可着色的。 该方法包括：如果节点装置的每个内部节点是可着色的，则产生用于制造半导体器件的彩色布局设计; 以及如果所述节点装置的至少一个内部节点不可着色，则修改所述布局。

    Lithographic Technique for Feature Cut by Line-End Shrink
    6.
    发明申请
    Lithographic Technique for Feature Cut by Line-End Shrink 有权
    通过线端收缩切割特征的平版印刷技术

    公开(公告)号：US20160181110A1

    公开(公告)日：2016-06-23

    申请号：US14835495

    申请日：2015-08-25

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yung-Sung Yen ,  Chun-Kuang Chen ,  Ko-Bin Kao ,  Ken-Hsien Hsieh ,  Ru-Gun Liu

    IPC分类号： H01L21/308 ,  H01L21/311 ,  H01L21/768 ,  H01L21/31

    CPC分类号： H01L21/0274 ,  H01L21/0228 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877

    摘要： A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a dataset specifying a plurality features to be formed on the workpiece. A first patterning of a hard mask of the workpiece is performed based on a first set of features of the plurality of features, and a first spacer material is deposited on a sidewall of the patterned hard mask. A second patterning is performed based on a second set of features, and a second spacer material is deposited on a sidewall of the first spacer material. A third patterning is performed based on a third set of features. A portion of the workpiece is selectively processed using a pattern defined by a remainder of at least one of the patterned hard mask layer, the first spacer material, or the second spacer material.

    摘要翻译： 提供了用于图案化诸如集成电路工件的工件的技术。 在示例性实施例中，该方法包括接收指定要在工件上形成的多个特征的数据集。 基于多个特征的第一组特征来执行工件的硬掩模的第一图案化，并且第一间隔物材料沉积在图案化硬掩模的侧壁上。 基于第二组特征进行第二图案化，并且第二间隔物材料沉积在第一间隔物材料的侧壁上。 基于第三组特征来执行第三图案化。 使用由图案化硬掩模层，第一间隔物材料或第二间隔物材料中的至少一个的剩余部分限定的图案来选择性地处理工件的一部分。

    Mask assignment optimization
    8.
    发明授权
    Mask assignment optimization 有权
    掩模分配优化

    公开(公告)号：US09003336B2

    公开(公告)日：2015-04-07

    申请号：US13781980

    申请日：2013-03-01

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Wen-Chun Huang ,  Ken-Hsien Hsieh ,  Ming-Hui Chih ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Ko-Bin Kao ,  Chii-Ping Chen ,  Dian-Hau Chen ,  Tsai-Sheng Gau ,  Burn Jeng Lin

    IPC分类号： G06F17/50 ,  H01L21/768

    CPC分类号： G06F17/50 ,  G03F1/44 ,  H01L21/76816

    摘要： A method for optimizing mask assignment for multiple pattern processes includes, through a computing system, defining which of a number of vias to be formed between two metal layers are critical based on metal lines interacting with the vias, determining overlay control errors for an alignment tree that defines mask alignment for formation of the two metal layers and the vias, and setting both the alignment tree and mask assignment for the vias so as to maximize the placement of critical vias on masks that have less overlay control error to the masks forming the relevant metal lines.

    摘要翻译： 用于优化多个图案处理的掩模分配的方法包括：通过计算系统，基于与通孔相互作用的金属线，确定要在两个金属层之间形成的多个通孔中的哪一个是至关重要的，确定对准树的覆盖控制误差 其定义用于形成两个金属层和通孔的掩​​模对准，并且设置用于通孔的对准树和掩模分配，以便最大化对具有较小重叠控制误差的掩模上的关键通孔的放置，以形成相关的掩模 金属线。

    Method of merging color sets of layout
    9.
    发明授权
    Method of merging color sets of layout 有权
    合并颜色集布局的方法

    公开(公告)号：US08943445B2

    公开(公告)日：2015-01-27

    申请号：US14104279

    申请日：2013-12-12

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Pi-Tsung Chen ,  Ming-Hui Chih ,  Ken-Hsien Hsieh ,  Wei-Long Wang ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Wen-Ju Yang ,  Gwan Sin Chang ,  Yung-Sung Yen

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： A method includes determining one or more potential merges corresponding to a color set Ai and a color set Aj of N color sets, represented by A1 to AN, used in coloring polygons of a layout of an integrated circuit. N is a positive integer, i and j are integers from 1 to N, and i≠j. One or more potential cuts corresponding to the color set Ai and the second color set Aj are determined. An index Aij is determined according to the one or more potential merges and the one or more potential cuts. A plurality of parameters F related to the index Aij is obtained based on various values of indices fi and fj. A parameter F is selected among the plurality of parameters F based on a definition of the index Aij.

    摘要翻译： 一种方法包括确定一个或多个与集成电路的布局的着色多边形中使用的颜色集合Ai和由A 1到AN表示的颜色集合A 1对应的潜在合并。 N是正整数，i和j是从1到N的整数，i≠j。 确定对应于颜色集合Ai和第二颜色集合Aj的一个或多个可能的剪切。 根据一个或多个潜在的合并和一个或多个潜在的切割来确定索引Aij。 基于索引fi和fj的各种值获得与索引Aij相关的多个参数F。 基于索引Aij的定义，在多个参数F中选择参数F.