发明申请
- 专利标题: METHODS FOR INTEGRATED CIRCUIT DESIGN AND FABRICATION
- 专利标题(中): 集成电路设计与制造方法
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申请号: US15174131申请日: 2016-06-06
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公开(公告)号: US20160293422A1公开(公告)日: 2016-10-06
- 发明人: Tsong-Hua Ou , Ken-Hsien Hsieh , Shih-Ming Chang , Wen-Chun Huang , Chih-Ming Lai , Ru-Gun Liu , Tsai-Sheng Gau
- 申请人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 主分类号: H01L21/033
- IPC分类号: H01L21/033
摘要:
The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.
公开/授权文献
- US09852908B2 Methods for integrated circuit design and fabrication 公开/授权日:2017-12-26
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