发明申请
US20160293422A1 METHODS FOR INTEGRATED CIRCUIT DESIGN AND FABRICATION 有权
集成电路设计与制造方法

METHODS FOR INTEGRATED CIRCUIT DESIGN AND FABRICATION
摘要:
The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.
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