公开(公告)号：US12199612B2

公开(公告)日：2025-01-14

申请号：US17858844

申请日：2022-07-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED

Inventor： Xing Chao Yin ,  Huaixin Xian ,  Hui-Zhong Zhuang ,  Yung-Chen Chien ,  Jerry Chang Jui Kao ,  Xiangdong Chen

IPC: H03K3/037 ,  H01L21/8238 ,  H01L27/092 ,  H03K17/687

Abstract: A semiconductor device includes: a cell region including active regions where components of transistors are formed; the cell region are arranged to function as a D flip-flop that includes a primary latch (having a first sleepy inverter and a first non-sleepy (NS) inverter), a secondary latch (having a second sleepy inverter and a second NS inverter), and a clock buffer (having third and fourth NS inverters). The transistors are grouped: a first group has a standard threshold voltage (Vt_std); a second group has a low threshold voltage (Vt_low); and an optional third group has a high threshold voltage (Vt_high). The transistors which comprise the first or second NS inverter have Vt_low. Alternatively, the transistors of the cell region are further arranged to function as a scan-insertion type of D flip-flop (SDFQ) that further includes a multiplexer; and the transistors of the multiplexer have Vt_low.

公开(公告)号：US12125792B2

公开(公告)日：2024-10-22

申请号：US18128742

申请日：2023-03-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Chi-Yu Lu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen

IPC: H01L23/535 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L27/02 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/5221 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/5386 ,  H01L27/0207 ,  H01L29/401 ,  H01L29/41725

Abstract: A method of forming a semiconductor device, includes forming an active region; forming first, second and third metal-to-drain/source (MD) contact structures which extend in a first direction, and correspondingly overlap and electrically couple to the active region; forming a via-to-via (V2V) rail which extends in a second direction perpendicular to the first direction, overlaps at least the first MD contact structure and the third MD contact structures; forming a first via-to-MD (VD) structure over, and electrically coupled to, the first MD contact structure and the V2V rail; and forming a first conductive segment which overlaps the V2V rail, is in a first metallization layer, and is electrically coupled to the first VD structure.

公开(公告)号：US12033935B2

公开(公告)日：2024-07-09

申请号：US17836896

申请日：2022-06-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Guo-Huei Wu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Cheng-Chi Chuang ,  Shang-Wen Chang ,  Yi-Hsun Chiu

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5283

Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.

公开(公告)号：US20240222269A1

公开(公告)日：2024-07-04

申请号：US18604071

申请日：2024-03-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Guo-Huei Wu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Cheng-Chi Chuang ,  Shang-Wen Chang ,  Yi-Hsun Chiu

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5283

Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.

公开(公告)号：US11983479B2

公开(公告)日：2024-05-14

申请号：US17885118

申请日：2022-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Ting-Wei Chiang ,  Jerry Chang-Jui Kao ,  Hui-Zhong Zhuang ,  Lee-Chung Lu ,  Li-Chun Tien ,  Meng-Hung Shen ,  Shang-Chih Hsieh ,  Chi-Yu Lu

IPC: G06F30/394 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/118

CPC classification number: G06F30/394 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11887

Abstract: A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.

公开(公告)号：US11973110B2

公开(公告)日：2024-04-30

申请号：US17313748

申请日：2021-05-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Che-Yuan Chang ,  Hui-Zhong Zhuang ,  Chih-Liang Chen

IPC: H01L29/06 ,  H01L49/02

CPC classification number: H01L29/0653 ,  H01L28/40

Abstract: A semiconductor structure includes a substrate and a first capacitor. The substrate includes an active region. The first capacitor is over the substrate and free from overlapping the active region from a top view perspective.

公开(公告)号：US11948886B2

公开(公告)日：2024-04-02

申请号：US17244058

申请日：2021-04-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Guo-Huei Wu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Li-Chun Tien

IPC: H01L23/528 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L23/5286 ,  H01L21/823475 ,  H01L29/0696

Abstract: A semiconductor device includes one or more active semiconductor components, wherein a front side is defined over the semiconductor substrate and a back side is defined beneath the semiconductor substrate. A front side power rail is formed at the front side of the semiconductor device and is configured to receive a first reference power voltage. First and second back side power rails are formed on the back side of the semiconductor substrate and are configured to receive corresponding second and third reference power voltages. The first, second and third reference power voltages are different from each other.

公开(公告)号：US11942420B2

公开(公告)日：2024-03-26

申请号：US17835281

申请日：2022-06-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Guo-Huei Wu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Cheng-Chi Chuang ,  Shang-Wen Chang ,  Yi-Hsun Chiu

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5283

Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.

公开(公告)号：US11764155B2

公开(公告)日：2023-09-19

申请号：US17728007

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Chun Tien ,  Chih-Liang Chen ,  Hui-Zhong Zhuang ,  Shun Li Chen ,  Ting Yu Chen

IPC: H01L23/528 ,  H01L27/092 ,  H01L21/8238 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5226 ,  H01L27/0924

Abstract: A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track.

公开(公告)号：US11552069B1

公开(公告)日：2023-01-10

申请号：US17463241

申请日：2021-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kuang-Ching Chang ,  Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Kuo-Nan Yang

IPC: H01L27/02 ,  G06F1/3287

Abstract: An integrated circuit includes a first, second and third power rail, and a header circuit coupled to a gated circuit. The gated circuit is configured to operate on a first or second voltage. The first and second power rail are on a back-side of a wafer, and extend in a first direction. The header circuit is configured to supply the first voltage to the gated circuit by the first power rail. The second power rail is separated from the first power rail in a second direction. The second power rail is configured to supply the second voltage to the gated circuit. The third power rail is on a front-side of the wafer and includes a first set of conductors extending in the second direction, and separated in the first direction. Each of the first set of conductors is configured to supply a third voltage to the header circuit.