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    Integrated circuit and method of forming the same
    1.
    发明授权
    Integrated circuit and method of forming the same 有权

    公开(公告)号：US11552069B1

    公开(公告)日：2023-01-10

    申请号：US17463241

    申请日：2021-08-31

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Kuang-Ching Chang ,  Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Kuo-Nan Yang

    IPC: H01L27/02 ,  G06F1/3287

    Abstract: An integrated circuit includes a first, second and third power rail, and a header circuit coupled to a gated circuit. The gated circuit is configured to operate on a first or second voltage. The first and second power rail are on a back-side of a wafer, and extend in a first direction. The header circuit is configured to supply the first voltage to the gated circuit by the first power rail. The second power rail is separated from the first power rail in a second direction. The second power rail is configured to supply the second voltage to the gated circuit. The third power rail is on a front-side of the wafer and includes a first set of conductors extending in the second direction, and separated in the first direction. Each of the first set of conductors is configured to supply a third voltage to the header circuit.

    Integrated circuit and method of forming the same
    2.
    发明授权
    Integrated circuit and method of forming the same 有权

    公开(公告)号：US12205941B2

    公开(公告)日：2025-01-21

    申请号：US17727338

    申请日：2022-04-22

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Kuang-Ching Chang ,  Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Chih-Liang Chen

    IPC: H01L27/02 ,  H01L23/522

    Abstract: An integrated circuit includes a set of active regions, a first set of contacts, a set of gates, a first set of power rails and a first set of vias. The set of active regions extends in a first direction. The first set of contacts overlaps the set of active regions, and a first and a second cell boundary of the integrated circuit that extends in a second direction. The set of gates extends in the second direction, overlaps the set of active regions, and is between the first and second cell boundary. The first set of power rails extends in the first direction, and overlaps at least the first set of contacts. The first set of vias electrically couples the first set of contacts and the first set of power rails together. The set of active regions extend continuously through the first cell boundary and the second cell boundary.

    Integrated circuit and method of forming the same
    3.
    发明授权
    Integrated circuit and method of forming the same 有权

    公开(公告)号：US11756952B2

    公开(公告)日：2023-09-12

    申请号：US18066154

    申请日：2022-12-14

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Kuang-Ching Chang ,  Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Kuo-Nan Yang

    IPC: H01L27/02 ,  G06F1/3287

    CPC classification number: H01L27/0207 ,  G06F1/3287

    Abstract: An integrated circuit includes a gated circuit configured to operate on a first or second voltage, a header circuit, a first power rail and a second power rail on a back-side of a wafer, a third power rail on the back-side of the wafer, and a fourth power rail on a front-side of the wafer. The first and second power rail extend in a first direction, and are separated from each other in a second direction. The third power rail is between the first and second power rail in the second direction. The third power rail is configured to supply the second voltage to the gated circuit. The fourth power rail includes a first set of conductors extending in the second direction. Each of the first set of conductors is configured to supply a third voltage to the header circuit, and is separated from each other in the first direction.

    Flip-flops having strong transistors and weak transistors
    5.
    发明授权
    Flip-flops having strong transistors and weak transistors 有权

    公开(公告)号：US12218670B2

    公开(公告)日：2025-02-04

    申请号：US18333402

    申请日：2023-06-12

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： I-Wen Wang ,  Po-Chih Cheng ,  Jia-Hong Gao ,  Kuang-Ching Chang ,  Tzu-Ying Lin ,  Jerry Chang Jui Kao

    IPC: H03K3/3562

    Abstract: An integrated circuit includes a first clocked forwarding-switch and a second clocked forwarding-switch each implemented with strong transistors in at least one strong active-region structure. The integrated circuit also includes a first clocked inverter and a second clocked inverter each implemented with weak transistors in at least one weak active-region structure. The integrated circuit further includes a first inverter cross coupled with the first clocked inverter and a second inverter cross coupled with the second clocked inverter. An output of the first clocked forwarding-switch is conductively connected with an output of the first clocked inverter, and an output of the second clocked forwarding-switch is conductively connected with an output of the second clocked inverter.

    Integrated circuit and method of forming the same
    6.
    发明授权
    Integrated circuit and method of forming the same 有权

    公开(公告)号：US12199615B2

    公开(公告)日：2025-01-14

    申请号：US18309217

    申请日：2023-04-28

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Yueh Chiang ,  Shang-Hsuan Chiu ,  Ming-Xiang Lu ,  Kuang-Ching Chang

    IPC: H03K3/356 ,  G06F30/39 ,  H01L27/02 ,  H01L27/092 ,  H03K3/3562 ,  H03K19/20

    Abstract: A flip-flop includes a first input circuit, a first NOR logic gate, a stacked gate circuit, a first NAND logic gate and an output circuit. The first input circuit generates a first signal responsive to at least a first data signal, a first or a second clock signal. The first NOR logic gate is coupled between a first and a second node, and generates a second signal responsive to the first signal and a first reset signal. The stacked gate circuit is coupled between the first and a third node, and generates a third signal responsive to the first signal. The first NAND logic gate is coupled between the third and a fourth node, and generates a fourth signal responsive to the third signal and a second reset signal. The output circuit is coupled to the fourth node, and generates a first output signal responsive to the fourth signal.

    Integrated circuit and method of forming the same
    7.
    发明授权
    Integrated circuit and method of forming the same 有权

    公开(公告)号：US12033998B2

    公开(公告)日：2024-07-09

    申请号：US18363230

    申请日：2023-08-01

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Kuang-Ching Chang ,  Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Kuo-Nan Yang

    IPC: H01L27/02 ,  G06F1/3287

    CPC classification number: H01L27/0207 ,  G06F1/3287

    Abstract: An integrated circuit includes a gated circuit configured to operate on at least a first or a second voltage, a header circuit coupled to the gated circuit, a first and second power rail on a back-side of a wafer, and a third power rail on a front-side of the wafer. The header circuit is configured to supply the first voltage to the gated circuit by the first power rail. The first power rail includes a first portion, a second portion and a third portion, the third portion being between the first portion and the second portion. The second power rail is configured to supply the second voltage to the gated circuit, and is between the first portion and the second portion. The third power rail includes a first set of conductors. Each of the first set of conductors being configured to supply a third voltage to the header circuit.

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