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    Isolation circuit between power domains
    2.
    发明授权
    Isolation circuit between power domains 有权

    公开(公告)号：US11526647B2

    公开(公告)日：2022-12-13

    申请号：US17115436

    申请日：2020-12-08

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chi-Yu Lu ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Jerry Chang Jui Kao ,  Pin-Dai Sue ,  Jiun-Jia Huang ,  Yu-Ti Su ,  Wei-Hsiang Ma

    IPC分类号： G06F30/394 ,  G03F1/70 ,  G03F1/36 ,  G06F30/398

    摘要： An integrated circuit includes a first type-one transistor, a second type-one transistor, a first type-two transistor, a second type-two transistor, a third type-one transistor, a fourth type-one transistor, and a fifth type-one transistor. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The first active-region of the third type-one transistor is connected with an active-region of the first type-one transistor. The second active-region and the gate of the third type-one transistor are connected together. The first active-region of the fifth type-one transistor is connected with the gate of the third type-one transistor. The second active-region of the fifth type-one transistor is configured to have a first supply voltage of a second power supply.

    TIE OFF DEVICE
    4.
    发明申请
    TIE OFF DEVICE 有权

    公开(公告)号：US20220352166A1

    公开(公告)日：2022-11-03

    申请号：US17863175

    申请日：2022-07-12

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Shao-Lun Chien ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Pin-Dai Sue

    IPC分类号： H01L27/092 ,  H01L23/528 ,  H01L23/522 ,  H01L21/765 ,  H01L21/8238

    摘要： An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first threshold voltage (VT). A second transistor includes the first active area and a second one of the gates. The second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor, and includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.

    FLIP-FLOP WITH DELINEATED LAYOUT FOR REDUCED FOOTPRINT
    6.
    发明申请
    FLIP-FLOP WITH DELINEATED LAYOUT FOR REDUCED FOOTPRINT 有权

    公开(公告)号：US20210297068A1

    公开(公告)日：2021-09-23

    申请号：US17339121

    申请日：2021-06-04

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chi-Lin Liu ,  Ting-Wei Chiang ,  Jerry Chang-Jui Kao ,  Hui-Zhong Zhuang ,  Lee-Chung Lu ,  Shang-Chih Hsieh ,  Che Min Huang

    IPC分类号： H03K3/3562 ,  G01R31/3185 ,  H01L27/092

    摘要： In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter. The slave switch circuitry and the second clock inverter circuit are disposed on a third line that is in parallel with and spaced apart from the second line.

    Method of designing an integrated circuit and integrated circuit
    8.
    发明授权
    Method of designing an integrated circuit and integrated circuit 有权

    公开(公告)号：US11074390B2

    公开(公告)日：2021-07-27

    申请号：US16512062

    申请日：2019-07-15

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chien-Hsing Li ,  Ting-Wei Chiang ,  Jung-Chan Yang ,  Ting Yu Chen

    IPC分类号： G06F30/394 ,  G06F30/392

    摘要： A method includes reserving a routing track within a cell, the cell includes signal lines for connection to elements within the cell, the cell further includes a plurality of routing tracks, the reserved routing track is one of the plurality of routing tracks, and the reserved routing track is free of the signal lines. The method includes placing the cell in a chip-level layout, wherein the chip-level layout includes a plurality of power rails. The method includes determining whether any of the plurality of power rails overlaps with any of the plurality of routing tracks other than the reserved routing track. The method includes adjusting a position of the cell in the chip-level layout in response to a determination that at least one power rail of the plurality of power rails overlaps with at least one routing track of the plurality of routing tracks other than the reserved routing track.