公开(公告)号：US09911823B2

公开(公告)日：2018-03-06

申请号：US15423945

申请日：2017-02-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Sanjay C. Mehta ,  Balasubramanian S. Pranatharthiharan ,  Ruilong Xie

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/033

CPC classification number: H01L29/4983 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76205 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/42368 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of filling trenches between gates includes forming a first and a second dummy gate over a substrate, the first and second dummy gates including a sacrificial gate material and a hard mask layer; forming a first gate spacer along a sidewall of the first dummy gate and a second gate spacer along a sidewall of the second dummy gate; performing an epitaxial growth process to form a source/drain on the substrate between the first and second dummy gates; disposing a conformal liner over the first and second dummy gates and the source/drain; disposing an oxide on the conformal liner between the first and second dummy gates; recessing the oxide to a level below the hard mask layers of the first and second dummy gates to form a recessed oxide; and depositing a spacer material over the recessed oxide between the first dummy gate and the second dummy gate.

公开(公告)号：US09899259B2

公开(公告)日：2018-02-20

申请号：US15443523

申请日：2017-02-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L21/027 ,  H01L29/66 ,  H01L23/535 ,  H01L27/11 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

公开(公告)号：US20180047615A1

公开(公告)日：2018-02-15

申请号：US15232341

申请日：2016-08-09

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Thomas J. Haigh ,  Juntao Li ,  Eric G. Liniger ,  Sanjay C. Mehta ,  Son V. Nguyen ,  Chanro Park ,  Tenko Yamashita

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/02 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/76852 ,  H01L23/528 ,  H01L23/5329 ,  H01L29/41775 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.

公开(公告)号：US20170278753A1

公开(公告)日：2017-09-28

申请号：US15618880

申请日：2017-06-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L27/11 ,  H01L29/66 ,  H01L23/535 ,  H01L21/027 ,  H01L21/311

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

公开(公告)号：US09735248B2

公开(公告)日：2017-08-15

申请号：US15248002

申请日：2016-08-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Sanjay C. Mehta ,  Tenko Yamashita

IPC: H01L29/45 ,  H01L29/08 ,  H01L29/16 ,  H01L29/40 ,  H01L29/41 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L23/48 ,  H01L21/768 ,  H01L21/225 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/3065 ,  H01L21/311 ,  H01L29/167 ,  H01L21/285 ,  H01L23/485

CPC classification number: H01L29/456 ,  H01L21/225 ,  H01L21/2251 ,  H01L21/2252 ,  H01L21/2254 ,  H01L21/28518 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/495 ,  H01L29/516 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.

公开(公告)号：US20170162438A1

公开(公告)日：2017-06-08

申请号：US15432372

申请日：2017-02-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L27/11 ,  H01L29/66 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers.

公开(公告)号：US20170148895A1

公开(公告)日：2017-05-25

申请号：US15423945

申请日：2017-02-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Sanjay C. Mehta ,  Balasubramanian S. Pranatharthiharan ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/033 ,  H01L21/02

CPC classification number: H01L29/4983 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76205 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/42368 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of filling trenches between gates includes forming a first and a second dummy gate over a substrate, the first and second dummy gates including a sacrificial gate material and a hard mask layer; forming a first gate spacer along a sidewall of the first dummy gate and a second gate spacer along a sidewall of the second dummy gate; performing an epitaxial growth process to form a source/drain on the substrate between the first and second dummy gates; disposing a conformal liner over the first and second dummy gates and the source/drain; disposing an oxide on the conformal liner between the first and second dummy gates; recessing the oxide to a level below the hard mask layers of the first and second dummy gates to form a recessed oxide; and depositing a spacer material over the recessed oxide between the first dummy gate and the second dummy gate.

公开(公告)号：US20170084712A1

公开(公告)日：2017-03-23

申请号：US15179393

申请日：2016-06-10

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Sanjay C. Mehta ,  Balasubramanian S. Pranatharthiharan ,  Ruilong Xie

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/4983 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76205 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/42368 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of filling trenches between gates includes forming a first and a second dummy gate over a substrate, the first and second dummy gates including a sacrificial gate material and a hard mask layer; forming a first gate spacer along a sidewall of the first dummy gate and a second gate spacer along a sidewall of the second dummy gate; performing an epitaxial growth process to form a source/drain on the substrate between the first and second dummy gates; disposing a conformal liner over the first and second dummy gates and the source/drain; disposing an oxide on the conformal liner between the first and second dummy gates; recessing the oxide to a level below the hard mask layers of the first and second dummy gates to form a recessed oxide; and depositing a spacer material over the recessed oxide between the first dummy gate and the second dummy gate.

公开(公告)号：US20170033188A1

公开(公告)日：2017-02-02

申请号：US15248095

申请日：2016-08-26

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Sanjay C. Mehta ,  Tenko Yamashita

IPC: H01L29/40 ,  H01L21/3065 ,  H01L29/45 ,  H01L21/285 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/456 ,  H01L21/225 ,  H01L21/2251 ,  H01L21/2252 ,  H01L21/2254 ,  H01L21/28518 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/495 ,  H01L29/516 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.

Abstract translation: 半导体器件包括设置在衬底上的栅极; 栅极的相对侧上的源极区域和漏极区域; 以及在所述源极区域和所述漏极区域中的至少一个的界面层部分上方并邻接一对沟槽接触部; 其中所述界面层包括在约5×10 21至约5×102 2原子/ cm 2范围内的量的硼。

公开(公告)号：US09558934B2

公开(公告)日：2017-01-31

申请号：US14925372

申请日：2015-10-28

Applicant: International Business Machines Corporation

Inventor： Donald Francis Canaperi ,  Alfred Grill ,  Sanjay C. Mehta ,  Son Van Nguyen ,  Deepika Priyadarshini ,  Hosadurga Shobha ,  Matthew T. Shoudy

IPC: H01L21/469 ,  H01L21/02 ,  H01L23/532 ,  H01L29/51 ,  C23C16/34 ,  C23C16/40 ,  C23C16/455 ,  H01L23/522 ,  H01L23/528 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L23/485

CPC classification number: H01L21/02274 ,  C23C16/345 ,  C23C16/401 ,  C23C16/45523 ,  C23C16/45525 ,  C23C16/50 ,  H01L21/02123 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02214 ,  H01L21/02219 ,  H01L21/02299 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53276 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/42364 ,  H01L29/4983 ,  H01L29/511 ,  H01L29/513 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films.