公开(公告)号：US08334169B2

公开(公告)日：2012-12-18

申请号：US13095680

申请日：2011-04-27

申请人： Reza Argenty Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

发明人： Reza Argenty Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/3128 ,  H01L21/76898 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit having an active side and a non-active side; forming a channel through the integrated circuit; forming an indent, having a flange and an indent side, from a peripheral region of the non-active side; and forming a conformal interconnect, having an offset segment, a sloped segment, and a flange segment, under the indent.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供具有有源侧和非有源侧的集成电路; 通过集成电路形成通道; 从非活动侧的周边区域形成具有凸缘和凹口侧的凹口; 以及在缩进下形成具有偏移段，倾斜段和凸缘段的共形互连。

公开(公告)号：US20120104562A1

公开(公告)日：2012-05-03

申请号：US13349510

申请日：2012-01-12

申请人： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

发明人： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC分类号： H01L23/48

CPC分类号： H01L23/5386 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/83 ,  H01L2924/00012

摘要： A semiconductor die has a first semiconductor die mounted to a carrier. A plurality of conductive pillars is formed over the carrier around the first die. An encapsulant is deposited over the first die and conductive pillars. A first stepped interconnect layer is formed over a first surface of the encapsulant and first die. The first stepped interconnect layer has a first opening. A second stepped interconnect layer is formed over the first stepped interconnect layer. The second stepped interconnect layer has a second opening. The carrier is removed. A build-up interconnect structure is formed over a second surface of the encapsulant and first die. A second semiconductor die over the first semiconductor die and partially within the first opening. A third semiconductor die is mounted over the second die and partially within the second opening. A fourth semiconductor die is mounted over the second stepped interconnect layer.

公开(公告)号：US08168458B2

公开(公告)日：2012-05-01

申请号：US12329800

申请日：2008-12-08

申请人： Byung Tai Do ,  Reza A. Pagaila ,  Linda Pei Ee Chua

发明人： Byung Tai Do ,  Reza A. Pagaila ,  Linda Pei Ee Chua

IPC分类号： H01L21/00

CPC分类号： H01L23/4952 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3107 ,  H01L23/3185 ,  H01L23/49541 ,  H01L24/05 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/02333 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/056 ,  H01L2224/1134 ,  H01L2224/1308 ,  H01L2224/16 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/4848 ,  H01L2224/48992 ,  H01L2224/49111 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L2224/85001 ,  H01L2224/85051 ,  H01L2224/85951 ,  H01L2224/85986 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01031 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2224/85186 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2224/4554

摘要： A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.

摘要翻译： 半导体晶片包含多个半导体管芯，每个半导体管芯具有围绕管芯的周边区域。 具有倾斜或垂直侧壁的凹陷区域形成在周边区域中。 在凹陷区域中形成导电层。 在半导体管芯的接触焊盘上形成第一螺柱凸块。 在凹陷区域内的第一导电层上方形成第二凸起凸块。 在第一和第二突起之间形成接合线。 在接合线和第一凸起凸起上形成第三个凸起凸块。 通过外围区域部分地形成的切割通道。 半导体晶片经历对切割通道的后研磨，以切割半导体晶片并分离半导体管芯。 半导体管芯可以配置在具有其它部件的半导体封装中，并且通过接合线和柱形凸起电互连。

公开(公告)号：US08143098B2

公开(公告)日：2012-03-27

申请号：US12411040

申请日：2009-03-25

申请人： Byung Tai Do ,  Linda Pei Ee Chua ,  Sharon Ooi ,  Reza Argenty Pagaila

发明人： Byung Tai Do ,  Linda Pei Ee Chua ,  Sharon Ooi ,  Reza Argenty Pagaila

IPC分类号： H01L21/00

CPC分类号： H01L21/563 ,  H01L22/32 ,  H01L23/3107 ,  H01L23/552 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: providing an interposer having device contacts, interconnect contacts, and test pads including the interconnect contacts along an interconnect perimeter region of the interposer, the device contacts at a device perimeter region of the interposer with the device perimeter region within the interior of the interconnect perimeter region, and the test pads at a test perimeter region of the interposer with the test perimeter region encompassing the device perimeter region; and mounting an integrated circuit over the device contacts.

摘要翻译： 一种制造集成电路封装系统的方法包括：提供具有器件触点，互连触点和测试焊盘的插入件，所述测试焊盘包括沿插入器的互连周边区域的互连触点，该器件在插入器的器件周边区域处接触， 所述互连周边区域内部的所述设备周边区域以及所述插入器的测试周边区域处的所述测试焊盘与所述测试周边区域包围所述器件周边区域; 并在设备触点上安装集成电路。

公开(公告)号：US08119447B2

公开(公告)日：2012-02-21

申请号：US12486271

申请日：2009-06-17

申请人： Reza Argenty Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

发明人： Reza Argenty Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/34 ,  H01L23/48

CPC分类号： H01L23/3128 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L29/0657 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a structure having a via filled with conductive material completely through the structure, a recess, and a pedestal portion bordering the recess; mounting a semiconductor device inside the recess in the structure; and encapsulating the structure and the semiconductor device in an encapsulation.

摘要翻译： 一种集成电路封装系统的制造方法，其特征在于：提供一种结构体，该结构具有通过所述结构完全通过导电材料填充的通孔，凹部和与所述凹部接合的基座部分; 将半导体器件安装在结构中的凹部内; 并将结构和半导体器件封装在封装中。

公开(公告)号：US20120018866A1

公开(公告)日：2012-01-26

申请号：US13188456

申请日：2011-07-21

申请人： Zigmund Ramirez Camacho ,  Henry Descalzo Bathan ,  Emmanuel Espiritu ,  Byung Tai Do ,  Arnel Senosa Trasporto ,  Linda Pei Ee Chua

发明人： Zigmund Ramirez Camacho ,  Henry Descalzo Bathan ,  Emmanuel Espiritu ,  Byung Tai Do ,  Arnel Senosa Trasporto ,  Linda Pei Ee Chua

IPC分类号： H01L23/495 ,  H01L21/56

CPC分类号： H01L21/4832 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having an upper hole below a paddle top side, the upper hole bounded by an upper non-horizontal side with a curve surface; forming a terminal adjacent the package paddle; mounting an integrated circuit on the paddle top side; and forming an encapsulation within the upper hole.

摘要翻译： 一种制造集成电路封装系统的方法，包括：提供一个封装桨叶，其具有在桨叶顶侧下方的上孔，所述上孔由具有曲面的上非水平侧限定; 形成邻近包装桨的端子; 将集成电路安装在桨叶顶侧; 并在上孔内形成封装。

公开(公告)号：US08080882B2

公开(公告)日：2011-12-20

申请号：US12641958

申请日：2009-12-18

申请人： Byung Tai Do ,  Heap Hoe Kuan ,  Reza A. Pagaila ,  Linda Pei Ee Chua

发明人： Byung Tai Do ,  Heap Hoe Kuan ,  Reza A. Pagaila ,  Linda Pei Ee Chua

IPC分类号： H01L23/544

CPC分类号： H01L24/82 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/24 ,  H01L24/48 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/82001 ,  H01L2224/82039 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor die has a peripheral region around the die. An insulating layer is formed over the semiconductor die. A portion of the insulating layer and peripheral is removed to form a recess around the semiconductor die. A conductive layer is deposited over the insulating layer and recess. The conductive layer is electrically connected to contact pads on the semiconductor die and conforms to a step into the recess. A gap is created through the conductive layer and peripheral region around the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. The conductive THV is recessed with respect to a surface of the semiconductor die. The conductive THV is electrically connected to the conductive layer.

摘要翻译： 半导体管芯具有围绕管芯的周边区域。 在半导体管芯上形成绝缘层。 去除绝缘层和周边的一部分以在半导体管芯周围形成凹陷。 导电层沉积在绝缘层和凹部上。 导电层电连接到半导体管芯上的接触焊盘，并符合入凹槽的步骤。 通过半导体管芯周围的导电层和周边区域产生间隙。 绝缘材料沉积在间隙中。 绝缘材料的一部分被去除以形成通孔（THV）。 导电材料沉积在THV中以形成导电THV。 导电THV相对于半导体管芯的表面凹陷。 导电THV与导电层电连接。

公开(公告)号：US07994624B2

公开(公告)日：2011-08-09

申请号：US12237344

申请日：2008-09-24

申请人： Linda Pei Ee Chua ,  Byung Tai Do ,  Reza Argenty Pagaila

发明人： Linda Pei Ee Chua ,  Byung Tai Do ,  Reza Argenty Pagaila

IPC分类号： H01L23/02

CPC分类号： H01L24/48 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L24/29 ,  H01L24/49 ,  H01L24/73 ,  H01L25/03 ,  H01L2224/05554 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An integrated circuit package system includes attaching an adhesive segment spacer to an interposer assembly; mounting an integrated circuit over a carrier; mounting the interposer assembly over the integrated circuit with the adhesive segment spacer exposing an inner region of the integrated circuit and covering a periphery of the integrated circuit; and forming an encapsulation over the integrated circuit, the interposer assembly, and the adhesive segment spacer with the interposer assembly exposed with a recess in the encapsulation.

摘要翻译： 集成电路封装系统包括将粘合剂段隔离件附接到插入件组件; 在载体上安装集成电路; 将所述插入器组件安装在所述集成电路上，所述粘合剂段间隔件暴露所述集成电路的内部区域并覆盖所述集成电路的外围; 以及在所述集成电路，所述插入器组件和所述粘合剂段间隔件之间形成封装，所述插入器组件在所述封装中暴露有凹部。

公开(公告)号：US20110187005A1

公开(公告)日：2011-08-04

申请号：US12699482

申请日：2010-02-03

申请人： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

发明人： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC分类号： H01L23/538 ,  H01L21/56

CPC分类号： H01L25/50 ,  H01L21/563 ,  H01L23/315 ,  H01L23/66 ,  H01L24/73 ,  H01L25/00 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/81805

摘要： A semiconductor wafer has a plurality of first semiconductor die with a stress sensitive region. A masking layer or screen is disposed over the stress sensitive region. An underfill material is deposited over the wafer. The masking layer or screen prevents formation of the underfill material adjacent to the sensitive region. The masking layer or screen is removed leaving a cavity in the underfill material adjacent to the sensitive region. The semiconductor wafer is singulated into the first die. The first die can be mounted to a build-up interconnect structure or to a second semiconductor die with the cavity separating the sensitive region and build-up interconnect structure or second die. A bond wire is formed between the first and second die and an encapsulant is deposited over the first and second die and bond wire. A conductive via can be formed through the first or second die.

摘要翻译： 半导体晶片具有多个具有应力敏感区域的第一半导体管芯。 掩模层或屏幕设置在应力敏感区域上方。 底部填充材料沉积在晶片上。 掩蔽层或屏幕防止邻近敏感区域形成底部填充材料。 去除掩模层或屏幕，留下邻近敏感区域的底部填充材料中的空腔。 将半导体晶片分割成第一模具。 第一管芯可以安装到堆积互连结构或第二半导体管芯，其中空腔分离敏感区域并建立互连结构或第二管芯。 在第一和第二管芯之间形成接合线，并且密封剂沉积在第一和第二管芯和接合线上。 可以通过第一或第二管芯形成导电通孔。

公开(公告)号：US07952176B2

公开(公告)日：2011-05-31

申请号：US12331347

申请日：2008-12-09

申请人： Reza Argenty Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

发明人： Reza Argenty Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC分类号： H01L23/495

CPC分类号： H01L23/3128 ,  H01L21/76898 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes providing an integrated circuit having an active side and a non-active side; forming a channel through the integrated circuit; forming an indent, having a flange and an indent side, from a peripheral region of the non-active side; and forming a conformal interconnect, having an offset segment, a sloped segment, and a flange segment, under the indent.

摘要翻译： 一种集成电路封装系统的制造方法，包括提供具有有源侧和非有源侧的集成电路; 通过集成电路形成通道; 从非活动侧的周边区域形成具有凸缘和凹口侧的凹口; 以及在缩进下形成具有偏移段，倾斜段和凸缘段的共形互连。